JPS6041491B2 - Digital waveform shaping filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform shaping filter used to remove intersymbol interference in pulse transmission.

In recent years, there has been a tremendous trend toward digitalization of equipment.
Many analog devices are being digitized. Although several proposals have been put into practical use regarding waveform shaping filters for conventional pulse transmission, the reality is that they are large in scale and are constructed entirely of analog elements.

An object of the present invention is to provide an efficient digital waveform shaping filter with a simple configuration.

The digital waveform shaping filter of the present invention can be used in a pulse transmission device that transmits pulses every T seconds.
Divide the impulse response of the waveform shaping filter into N time intervals (N is a positive integer), divide the time interval into M equal parts (M is a positive integer), and calculate the impulse response corresponding to the M equal divided small time intervals. - Quantize the amplitude value of the response and store it in the N storage devices that store the name mi (i = 1 to M) of the time interval as the call address and count the clocks generated at intervals of voice seconds. and an M-value counter that supplies the counted value to each of the N storage devices as a call address mi (i=1 to M), and an input terminal by a pulse output from the M-value counter every M clocks. an N-stage shift register that sequentially inputs and shifts transmission data from the N-stage shift register;
and a digital-to-analog converter that converts the output of the pre-product circuit into an analog signal. A digital waveform shaping filter that outputs a transmission waveform from the output of the digital-to-analog converter is obtained.

According to this invention, the waveform shaping filter is completely digitalized, and can respond to changes in transmission speed by simply changing the clock frequency of the device, and can be sufficiently miniaturized.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows the impulse response of the waveform shaping filter according to the present invention for 4T seconds with a time interval N of 4. It is assumed that the addressing is performed sequentially from the right side to the left side in the figure. Considering that the impulse response converges in NT seconds, the output of the waveform shaping filter is determined by the N input data and the impulse response for the NT seconds. If the impulse response is f(t), then the filter output g(t) is a
It is expressed as N pieces of input data such as m: (a-亥"heat...a亥"). FIG. 2 is a diagram showing a first embodiment of the present invention, and is a concrete example of the above equation.

First, memory ROM13, 12, 11, 10 for discussion only
1, regions 1, 2, 3, and 4 of the impulse response of the filter shown in FIG. 1 are stored for T seconds. The M-value counter 40 receives a clock from a clock generator 50 that generates a clock M times the transmission rate. It counts the number of blocks and supplies the contents to the ROMs 13, 12, 11, and 10 as call addresses. Taking the output of the ROM-10 as an example, the waveform in area 4 in FIG. 1 is repeatedly output with accuracy at a cycle of T seconds. A 4-stage shift register with N being 4 is used as an N-stage shift register.Data 1 is input one after another from the input terminal 100 using pulses from the M-value counter 40, and is shifted to the left. The input from the input terminal is a binary value of 1, 0. 4th stage of shift register and ROM-1 0, 3rd stage and ROM-1 1st and 2nd stage and R
The outputs of the first stage of the OM-12 and the ROM-13 are multiplied, but since the data is binary, the AND gate arrays 20, 21, 22, and 23 may be used as the interpolators. In other words, if the contents of the fourth stage of the shift 1 register are 1, the output of the ROM-10 is output as is to the output of the AND gate column 20, and if it is 0, the output of the AND gate column 20 is lined with zeros. It turns out. These AND gate columns 20
, 21, 22, and 23 are added by an adder 24 and applied to a digital-to-analog converter 60. The converted signal is passed through a suitable low-pass filter 70 and sent to an output terminal 200 after removing steps due to doji conversion. 600' shows a product-sum circuit, which performs N products and their additions. Next, in order to explain the operation of this embodiment shown in FIG. 2, an impulse 1000 . . . is applied to the input terminal 100.

In the initial state, the contents of the shift register 30 are all zeros. Therefore, the output terminal 200 is also zero. The pulse of the M-value counter 40 indicates “1” in the first stage of the shift register.
is input. Only the output of the ROM-13 is output from the output terminal 200 in accordance with changes in the contents of the M-value counter 40. When the M value counter 40 counts M clocks, the "1" in the first stage of the shift register is sent to the second stage. Therefore, the contents of ROM-12 are now output to the output terminal 200.
appears in Similarly, each time the M-value counter 40 counts M clocks, the contents of ROM-10 are output one after another, and when the "1" in the shift register finally disappears from the fourth stage, nothing is output from the output terminal. It won't come out. The above is the impulse response of this filter,
It can be seen that by inputting actual data 1 to the input terminal, the impulse responses are superimposed and output to the output terminal 200 according to the 1 and 0 of data 1. FIG. 3 shows a second embodiment of the invention.

In this figure, shift register 30, M value counter 40
, ROMI0, 1, 1, 12, 13 digital-to-analog converter 60, and low-pass filter 7 are exactly the same as those shown in FIG. In this embodiment, the four multiplication circuits 20, 21, 22, 23 and the four-input addition circuit of the embodiment of FIG.
, 2-input adder circuit 120, data latch circuit 80,
81 constitutes the mirror sum circuit 500. First, the clock frequency of the clock generator 50 is increased from M times the transmission speed to M×N times the transmission speed. This is the same as in the first embodiment, since the clock is added to the M-value counter after passing through the N-value counter 130. First, N value counter (N=1
, 2, 3, 4) is 1, the signal is input to the next adder 120 through the signal switching device 110' or the output of the ROM-13. The output of adder 120 is read into data latch circuit 80 because the clock from clock generator 50 is applied as an input signal to data latch circuit 80 through delay circuit 90. At this time, shift
The first stage of the register 30 (Fig. 3 Shift register 30
From the right to the left, the first row, second row, etc. ) is “0”
”, the ROM-13 outputs zero. That is, the next
When the content of the value counter reaches 2, the signal switching device 110' passes the output of the ROM-12. At this time, shift
If the contents of the second row of the register are “0”, ROM-
12 has zero output. The next output of adder 120 is the sum of the output of data latch 80, in which the output from ROM-13 is stored, and the output of ROM-12. This sum is a pulse from the delay circuit 90 and the data 1/latch 8
Read to 0. Similarly, the contents of ROM-11 and ROM-10 are added to the data latch 80 one after another until the N value counter reaches 4. N value counter becomes 4 and ROM-1
When the inputs from 0, 11, 12, and 13 are all added together, the next data is read into the latch 81. At this time, the contents of the data latch 80 are reset by a lowering pulse to the data latch 81, and are prepared for the next Enowa. As described above, the signal switching device 1 is used as the product 0 circuit.
10, 2 output adder 120, data 1/latch 80, 8
1. By using the delay circuit 90 and the N-value counter 130, when N becomes large, it is possible to cope with it by only slightly changing the signal switching device 110. In addition, if the signal switching device uses ROMI0, 11, 12, and 13 whose output terminals become high impedance depending on the control signal level (tri-state output), the contents of the four-value counter will be input to the demultiplexer and the The four outputs of the multiplexer can be applied to the control signal inputs of the ROMIs 0, 1 1, 12, 13, and the output of each ROM can be one directly striped output. (Wired Ower).
In this case, the signal switching device is simply a 1:N demultiplexer. As described above, in the digital waveform shaping filter of the present invention, even if N of the filter's in/V response NT seconds is considerably increased, the structure of the bag hawk does not suddenly increase in size, and it is easy to use with ordinary digital elements. Good characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the impulse response of the digital waveform shaping filter according to the present invention. FIG. 2 is a diagram showing a first embodiment of the invention, and FIG. 3 is a diagram showing a second embodiment of the invention. In the figure, 10,
1 1, 12, 13 are storage devices, 40 is an M-value counter, 30 is an N-stage shift register, and 60 is a digital
An analog converter, 500 a summation circuit, and 50 a clock generation circuit are shown, respectively. Oh figure 2 figure soup 3 figure

Claims (1)

[Claims] 1 In a pulse transmission device that transmits pulses every T seconds, the impulse response of a waveform shaping filter for NT seconds (N is a positive integer) is divided into N time intervals, and the time intervals are divided into M equal parts (M is a positive integer). (an integer), quantizes the amplitude value of the impulse response corresponding to the small time interval divided into M equal parts, and quantizes this into the name mi (i=1 to
M) is stored as a call address in N memory devices, and a clock generated at an interval of T/M seconds is counted, and the counted value is stored in each of the N memory devices as a call address mi.
An M-value counter supplied as (i=1 to M),
an N-stage shift register that sequentially inputs and shifts transmission data from an input terminal using pulses output from the M-value counter every M clocks;
a product-sum circuit that multiplies the N contents of the registers and the outputs of the N storage devices and adds the N products; and a digital-analog converter that converts the output of the product-sum circuit into an analog signal. 1. A digital waveform shaping filter, comprising: a converter, and obtains a transmission waveform from the output of the digital/analog converter.