MY155586A - System for increasing throughput for memory device - Google Patents

System for increasing throughput for memory device

Info

Publication number
MY155586A
MY155586A MYPI20080002A MYPI20080002A MY155586A MY 155586 A MY155586 A MY 155586A MY PI20080002 A MYPI20080002 A MY PI20080002A MY PI20080002 A MYPI20080002 A MY PI20080002A MY 155586 A MY155586 A MY 155586A
Authority
MY
Malaysia
Prior art keywords
memory device
throughput
memory
increasing throughput
buffer units
Prior art date
Application number
MYPI20080002A
Inventor
Mohamad Yusri Bin Mohamad Yusof
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Priority to MYPI20080002A priority Critical patent/MY155586A/en
Priority to PCT/MY2009/000002 priority patent/WO2009084943A2/en
Publication of MY155586A publication Critical patent/MY155586A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Abstract

THE PRESENT INVENTION PROVIDES A SYSTEM FOR INCREASING THE THROUGHPUT FOR A MEMORY SUBSYSTEM, IN PARTICULAR ON THAT INCLUDES A PIPELINED MEMORY DEVICE AND A NON-CACHED SINGLE-BUS PROCESSOR CORE. WITH THIS SYSTEM, TOTAL LATENCY OF THE MEMORY SUBSYSTEM IS REDUCED AND THUS THROUGHPUT IS INCREASED, SAID CONDITION IS ACHIEVED WITH THE INTRODUCTION OF A PLURALITY OF BUFFER UNITS, PREFERABLY AT LEAST TWO SLIDING BUFFERS WITHIN THE MEMORY CONTROLLER OF THE PRESENT INVENTION. SAID PLURALITY OF BUFFER UNITS IS CONFIGURED TO CAPTURE SPECULATIVE READS, THEREBY AVOIDS LATENCY IN THE MEMORY DEVICE. MOST ILLUSTRATIVE DRAWING:
MYPI20080002A 2008-01-02 2008-01-02 System for increasing throughput for memory device MY155586A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
MYPI20080002A MY155586A (en) 2008-01-02 2008-01-02 System for increasing throughput for memory device
PCT/MY2009/000002 WO2009084943A2 (en) 2008-01-02 2009-01-02 System for increasing throughput for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI20080002A MY155586A (en) 2008-01-02 2008-01-02 System for increasing throughput for memory device

Publications (1)

Publication Number Publication Date
MY155586A true MY155586A (en) 2015-11-03

Family

ID=40824924

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI20080002A MY155586A (en) 2008-01-02 2008-01-02 System for increasing throughput for memory device

Country Status (2)

Country Link
MY (1) MY155586A (en)
WO (1) WO2009084943A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10944697B2 (en) * 2019-03-26 2021-03-09 Microsoft Technology Licensing, Llc Sliding window buffer for minimum local resource requirements

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2335762C (en) * 1998-03-25 2008-01-10 Advanced Risc Mach Ltd Write buffering in a data processing apparatus
US6772315B1 (en) * 2001-05-24 2004-08-03 Rambus Inc Translation lookaside buffer extended to provide physical and main-memory addresses
US6934951B2 (en) * 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7346735B2 (en) * 2004-04-08 2008-03-18 Intel Corporation Virtualized load buffers
US20070250689A1 (en) * 2006-03-24 2007-10-25 Aris Aristodemou Method and apparatus for improving data and computational throughput of a configurable processor extension

Also Published As

Publication number Publication date
WO2009084943A2 (en) 2009-07-09
WO2009084943A3 (en) 2009-10-15

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