WO2009084943A3 - System for increasing throughput for memory device - Google Patents

System for increasing throughput for memory device Download PDF

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Publication number
WO2009084943A3
WO2009084943A3 PCT/MY2009/000002 MY2009000002W WO2009084943A3 WO 2009084943 A3 WO2009084943 A3 WO 2009084943A3 MY 2009000002 W MY2009000002 W MY 2009000002W WO 2009084943 A3 WO2009084943 A3 WO 2009084943A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
throughput
increasing throughput
present
memory
Prior art date
Application number
PCT/MY2009/000002
Other languages
French (fr)
Other versions
WO2009084943A2 (en
Inventor
Yusri Bin Mohamad Yusof Mohd
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2009084943A2 publication Critical patent/WO2009084943A2/en
Publication of WO2009084943A3 publication Critical patent/WO2009084943A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Abstract

The present invention provides a system for increasing the throughput for a memory subsystem, in particular one that includes a pipelined memory device and a non-cached single-bus processor core. With this system, total latency, of the memory subsystem is reduced and thus throughput is increased, said condition is achieved with the introduction of at least two sliding window buffers within the memory controller of the present invention.
PCT/MY2009/000002 2008-01-02 2009-01-02 System for increasing throughput for memory device WO2009084943A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI20080002 2008-01-02
MYPI20080002A MY155586A (en) 2008-01-02 2008-01-02 System for increasing throughput for memory device

Publications (2)

Publication Number Publication Date
WO2009084943A2 WO2009084943A2 (en) 2009-07-09
WO2009084943A3 true WO2009084943A3 (en) 2009-10-15

Family

ID=40824924

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2009/000002 WO2009084943A2 (en) 2008-01-02 2009-01-02 System for increasing throughput for memory device

Country Status (2)

Country Link
MY (1) MY155586A (en)
WO (1) WO2009084943A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10944697B2 (en) * 2019-03-26 2021-03-09 Microsoft Technology Licensing, Llc Sliding window buffer for minimum local resource requirements

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020038410A1 (en) * 1998-03-25 2002-03-28 Arm Limited Write buffer for use in a data processing apparatus
WO2003063018A2 (en) * 2002-01-17 2003-07-31 Intel Corporation Functional pipelines
US6772315B1 (en) * 2001-05-24 2004-08-03 Rambus Inc Translation lookaside buffer extended to provide physical and main-memory addresses
US20050228951A1 (en) * 2004-04-08 2005-10-13 Ramesh Peri Virtualized load buffers
US20070250689A1 (en) * 2006-03-24 2007-10-25 Aris Aristodemou Method and apparatus for improving data and computational throughput of a configurable processor extension

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020038410A1 (en) * 1998-03-25 2002-03-28 Arm Limited Write buffer for use in a data processing apparatus
US6772315B1 (en) * 2001-05-24 2004-08-03 Rambus Inc Translation lookaside buffer extended to provide physical and main-memory addresses
WO2003063018A2 (en) * 2002-01-17 2003-07-31 Intel Corporation Functional pipelines
US20050228951A1 (en) * 2004-04-08 2005-10-13 Ramesh Peri Virtualized load buffers
US20070250689A1 (en) * 2006-03-24 2007-10-25 Aris Aristodemou Method and apparatus for improving data and computational throughput of a configurable processor extension

Also Published As

Publication number Publication date
MY155586A (en) 2015-11-03
WO2009084943A2 (en) 2009-07-09

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