MY144758A - Printed circuit board and method of production thereof - Google Patents

Printed circuit board and method of production thereof

Info

Publication number
MY144758A
MY144758A MYPI0405101A MY144758A MY 144758 A MY144758 A MY 144758A MY PI0405101 A MYPI0405101 A MY PI0405101A MY 144758 A MY144758 A MY 144758A
Authority
MY
Malaysia
Prior art keywords
wiring patterns
production
circuit board
printed circuit
wiring
Prior art date
Application number
Inventor
Naohiro Hirose
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of MY144758A publication Critical patent/MY144758A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

A FILET F IS ADDED TO A PORTION CONSTITUTING A CORNER PORTION C EQUAL TO OR SMALLER THAN 90° IN A CROSSING PORTION X OF WIRING PATTERNS 58B, 58C AND 58D, AND A WIRING PATTERN 58 IS FORMED. SINCE THE FILET F IS ADDED, THE WIRING PATTERNS ARE NOT MADE THIN AND ARE NOT DISCONNECTION IS CAUSED IN THE WIRING PATTERNS AND NO AIR BUBBLES ARE LEFT BETWEEN THE CROSSING PORTION X OF THE WIRING PATTERNS AND AN INTERLAYER RESIN INSULATING LAYER SO THAT RELIBILITY OF A PRINTED WIRING BOARD IS IMPROVED.
MYPI0405101 1999-04-01 1999-06-15 Printed circuit board and method of production thereof MY144758A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9472599A JP4197070B2 (en) 1999-04-01 1999-04-01 Multilayer build-up wiring board

Publications (1)

Publication Number Publication Date
MY144758A true MY144758A (en) 2011-10-31

Family

ID=14118105

Family Applications (2)

Application Number Title Priority Date Filing Date
MYPI9902439 MY124070A (en) 1999-04-01 1999-06-15 Printed circuit board and method of production thereof
MYPI0405101 MY144758A (en) 1999-04-01 1999-06-15 Printed circuit board and method of production thereof

Family Applications Before (1)

Application Number Title Priority Date Filing Date
MYPI9902439 MY124070A (en) 1999-04-01 1999-06-15 Printed circuit board and method of production thereof

Country Status (2)

Country Link
JP (1) JP4197070B2 (en)
MY (2) MY124070A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004260133A (en) 2003-02-04 2004-09-16 Seiko Epson Corp Wiring board, electro-optical device, manufacturing method thereof and electronic apparatus
JP2007305653A (en) * 2006-05-09 2007-11-22 Toppan Printing Co Ltd Multilayer circuit wiring board and semiconductor device
JP5223213B2 (en) * 2007-03-12 2013-06-26 凸版印刷株式会社 Multilayer wiring board, semiconductor device package, and electronic equipment
JP5078687B2 (en) * 2007-03-22 2012-11-21 日本特殊陶業株式会社 Manufacturing method of multilayer wiring board
JP2009094361A (en) * 2007-10-10 2009-04-30 Nitto Denko Corp Cof board
US20130153275A1 (en) 2011-12-19 2013-06-20 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
JP5607710B2 (en) * 2011-12-19 2014-10-15 サムソン エレクトロ−メカニックス カンパニーリミテッド． Printed circuit board and printed circuit board manufacturing method
CN113474853B (en) * 2019-02-27 2023-04-04 住友电工印刷电路株式会社 Printed wiring board and method for manufacturing printed wiring board

Also Published As

Publication number Publication date
JP2000294925A (en) 2000-10-20
JP4197070B2 (en) 2008-12-17
MY124070A (en) 2006-06-30

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