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Priority claimed from IE2002/0315Aexternal-prioritypatent/IE83726B1/en
Application filed by Electro Scient Ind IncfiledCriticalElectro Scient Ind Inc
Publication of MY135361ApublicationCriticalpatent/MY135361A/en
Internal Circuitry In Semiconductor Integrated Circuit Devices
(AREA)
ing And Chemical Polishing
(AREA)
Abstract
A FORMATION (8) IN A FIRST OF A SUBSTRATE (5) IS MACHINED BY AN ULTRAVIOLET OR VISIBLE RADIATION LASER(9), TO A PREDETERMINED DEPTH THAT IS LESS THAN A FULL DEPTH OF THE SUBSTRATE; AND A MATERIAL IS REMOVED FROM A SECOND SURFACE OF THE SUBSTRATE OPPOSED TO THE FIRST SURFACE TO THE PREDETERMINED DEPTH FROM THE FIRST SURFACE TO COMMUNICATE WITH THE FORMATION. MATERIAL MAY BE REMOVED BY, FOR EXAMPLE, LAPPING AND POLISHING,CHEMICAL ECTHING,PLASMA ETCHING OR LASER ABLATION. THE INVENTION HAS APPLICATION IN, FOR EXAMPLE, DICING SEMICONDUCTOR WAFERS (1) OR FORMING METALLISED VIAS (10) IN WAFERS(1).FIG. 4(A),4(B),AND 4(C)