MXPA99007297A - Supply of energy for a diverter circuit that operates multip exploring frequencies - Google Patents

Abstract

A television set has the ability to selectively display information in images obtained from a broadcast television signal and a presentation monitor data signal. A voltage switch-mode switch power supply of zero (100) generates a higher voltage supply voltage B +, for a horizontal deviator circuit output stage (101), when the diverter circuit output stage operates at a speed greater than or equal to approximately 32 KHz. A power supply of step-type regulator (102) generates, at a common supply terminal (B +), a lower voltage supply voltage B +, when the diverter circuit output stage operates at a lower speed of approximately 16 KHz. During the ignition interval, the horizontal scan output stage is supplied with the lowest supply voltage B + without considering the scan frequency to reduce the excessive voltage in the horizontal output stage switching transistor to improve the operational reliability.

Description

POWER SUPPLY FOR A DIVERTER CIRCUIT THAT OPERATES MULTIPLE EXPLORING FREQUENCIES FIELD OF THE INVENTION The invention relates to a power supply for a bypass circuit output stage.

BACKGROUND OF THE INVENTION A television receiver may have the ability to selectively display information in images on the same color cathode ray tube (CRT) using a diverting current at different horizontal scanning frequencies. For example, when the information is displayed on images of a television signal according to a broadcast standard, it may be more economical to use a horizontal diverting current at a speed of approximately 16 KHz, referred to as the speed 1H. Whereas, when the information is displayed in images of a high-definition television signal or a display monitor data signal, the velocity of the horizontal diverting current may be equal to or greater than 32 KHz, referred to as 2nH, where n is equal to or greater than 1. It is well known to vary the magnitude of the supply voltage of the horizontal deflection circuit output stage, according to the selected horizontal velocity of the diverting current, to obtain similar image widths using the same winding horizontal derailleur. In a type of zero voltage switching (ZVS) of a switch mode power supply (SMPS), a power transistor is turned on when the voltage across its terminals is approximately zero. Advantageously, a ZVS SMPS supplies regulated voltage with high efficiency and low energy dissipation. When a wide range of supply voltages is required, such as a television receiver as discussed above, disadvantageously, a ZVS SMPS can not provide the voltage switching aspect at zero over the entire output voltage scale.

COMPENDIUM OF THE INVENTION According to one aspect of the invention, a first power supply, including a first power transistor, generates a supply voltage for a diverter circuit output stage, when the diverter circuit output stage operates at a first frequency diverter. A second power supply that includes a second power transistor generates a supply voltage when the diverter circuit output stage operates at a second diverter frequency. Each of the first and second power supply selectively generates its supply voltage in a common terminal. To carry out a further aspect of the invention, the first power supply operates as a ZVS SMPS. The ZVS SMPS supplies power when the deviating frequency is at a relatively narrow range of frequencies, such as 2nH. Whereas, the second power supply, for example, a step-regulator power supply in series, supplies the energy when the diverting frequency is at 1H. Therefore, advantageously, the ZVS SMPS operates on a substantially narrow scale of output voltages that without the power supply of step controller in series. Advantageously, since only one of the first and second power supplies selectively activates the output stage at any given time, the first and second power transistors may share a common thermal collector arrangement. Therefore, advantageously, the power removal capacity dissipated from the thermal collector arrangement does not need to exceed the requirement of only one of the energy transistors that dissipates the most energy. A display diverting apparatus, modeling one aspect of the invention, is capable of operating at a selected deviation frequency of a frequency scale. The apparatus includes a source of a synchronization signal at a frequency indicative of the selected frequency. A diverter circuit output stage responds to the synchronization signal to generate a diverting current at the selected diverter frequency. A first power supply that includes a first power transistor, is used to generate a first supply voltage through the operation of the first energy transistor when a first diverting frequency is selected. A second power supply including a second power transistor is used to generate a second power voltage through the operation of the second power transistor, when a second diverting frequency is selected. A source of a signal indicative of a frequency of the synchronization signal is used to generate a first control signal that is coupled to one of the first and second power supplies. The first supply voltage is selected, according to the first control signal, to energize the deviator circuit output stage when the first deviating frequency is selected. The second supply voltage is selected when the second diverter frequency is selected. When the first supply voltage energizes the output stage, the second power transistor is outside a supply current path of the output stage. When the second supply voltage energizes the output stage, the first energy transistor is outside the supply current path of the output stage.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A illustrates a horizontal derailleur circuit output stage selectively energized by a SMPS supply and a serial step regulator, according to one aspect of the invention; Figure 1B illustrates a control circuit of the arrangement of Figure 1A; and Figures 2A-2C illustrate waveforms useful in explaining the operation of the tuned SMPS supply of Figure 1A.

DETAILED DESCRIPTION Figure 1A illustrates a horizontal deflector circuit output stage 101 of a television receiver having multiple scanning frequency capability. Step 101, in accordance with one aspect of the invention, is selectively energized through a tuned switch mode power supply of a zero voltage switching type (ZVS) 100 and a pass-through power supply. in series 102. A driving stage 103 responds to an input signal 107a, at the selected horizontal scanning frequency, and generates a driving control signal 103a to control the operation of the switch of a switching transistor 104 of the output stage 101. The driving stage 103 is capable of providing a horizontal base current at controllable amplitudes over a wide frequency range. The collector of transistor 104 is coupled to a TOC terminal of a primary winding T0W1 of a retraction transformer TO. The end terminal TOC of winding T0W1 is coupled to a non-commutated return capacitor 105 and to a horizontal deviating winding LY having a fixed value to form a recoil resonant circuit, during the horizontal return interval, in a conventional manner. The extreme TOC terminal is also coupled to a conventional damper diode 108. A conventional bank of switched capacitors S 106 is coupled in series with the winding LY to selectively couple the capacitors S, not shown, to the LY winding, according to a signal of SCSEL selection control. In a standard receiver broadcasting mode of the television receiver, the frequency of a horizontal diverting current, iy, in the winding LY is at the speed 1H of approximately 16 KHz. In a high-definition television operating mode of the television receiver, the frequency of the horizontal diverting current, i, is 2.14 times greater, referred to as 2.14H. In a monitor operation mode, the frequency of the horizontal diverting current, iy, is selected from a scale of between 2H and 2.4H. The ZVS SMPS 100 generates a supply voltage B + which is coupled to the terminal T0B of the transformer T0 and includes a power transistor, Tr, metal oxide semiconductor (MOS) of type N, which operates as a transistor switch. The transistor Tr has a drain electrode coupled through a primary winding L1 of a transformer T1 to a terminal 20 of a direct current (DC) input supply voltage, RAWB. The RAWB voltage is derived from, for example, a filter capacitor coupled to a bridge rectifier that rectifies a main supply voltage, followed by a voltage regulator, not shown. A source electrode of transistor Tr is coupled to ground through a sampling resistor current sensor R12. A damping diode D6, operating as a switch, is coupled in parallel with the transistor Tr, and is included in the same package with the transistor Tr to form a bidirectional switch 22. A retraction capacitor C6 is coupled in parallel with the diode D6 and in series with a winding L1 of a transformer T1 to form, with a winding inductance L1, a resonant circuit 21 when the switch 22 is not conductive. A secondary winding L2 of the transformer T1 is coupled to a cathode of a peak rectifier diode D8 having an anode that is coupled to ground, to generate the supply voltage B + in a C10 filter capacitor, which is coupled to a terminal T1a of winding L2. The voltage B + is coupled to the TOB terminal of the winding T0W1. A diode D20 rectifies a voltage developed in a secondary winding T0W2 of a transformer TO to generate a voltage VFEDB that is proportional to the voltage B +. The voltage VFEDB is coupled to a voltage divider formed by the resistors R15 and R17. A VSENSE voltage is developed through a filter capacitor V36 that is coupled in parallel with the resistor R17. The voltage VSENSE is coupled to the base of a transistor Q4, of an error amplifier 23, through a secondary voltage divider including a resistor R35 and a series arrangement of a resistor R34, diodes D30, D31 and D32 . An emitting electrode of transistor Q4 is coupled through a gain determining resistor R16 to a Zener diode D9 which develops a reference voltage VREF of error amplifier 23. Diode D9 is energized through a resistor R13 from a supply voltage of 15V. A collector of transistor Q4 is coupled to a collector load resistor R30 and to a base of a common emitter amplifier transistor Q5 through a resistor R21. A resistor R32 of gain determination is coupled to the emitter of transistor Q5. The collector of transistor Q5 is coupled to a filter capacitor C30 and to a base of a comparator transistor Q2 via a resistor R33. An error collector current le from transistor Q5 is indicative of a difference between a portion of the voltage VSENSE and reference voltage VREF.

A voltage VR12, developed in the current sensing resistor R12 is coupled via a resistor R11 to a base electrode of the comparing transistor Q2. The transistor Q2 is turned on, during each cycle, when a base voltage VBQ2 of the transistor Q2 becomes equal to the forward voltage of the base-emitter junction of the transistor Q2. The voltage VBQ2 includes a first portion that is proportional to a drain current of source ID in the transistor Tr. An error feedback voltage V2 on the capacitor C30 is coupled via the resistor R33 to the base of the transistor Q2 to develop a second voltage portion VBQ2. The collector electrode of transistor Q2 is coupled to the base electrode of a transistor Q1 and the collector electrode of transistor Q1 is coupled to the base electrode of a transistor Q2 to form a regeneration switch 31. A control voltage, VG, of transistor Tr is developed in the emitter of the transistor Q1 which forms an output terminal of the regeneration switch 31 and is coupled to the gate electrode of the transistor Tr via a resistor R10. A secondary winding L3 of the transformer T1 is coupled via a resistor R9 to produce an alternating current (AC) voltage V1. The voltage V1 is coupled AC through a capacitor C4 and a resistor R8 to the emitter of the transistor Q1 to generate the driving voltage VG of the transistor Tr. The coupled voltage AC, V1, is coupled via a collector resistor R7 to the collector electrode of transistor Q2 and to the base electrode of transistor Q1. A resistor R3 coupled between the + 15V supply voltage source and a terminal 30 the capacitor C4 which is far from the winding L3, charges the capacitor C4 after activation or ignition. When the voltage VG on the transistor gate electrode Tr exceeds a threshold voltage of the MOS transistor Tr, the transistor Tr leads causing a reduction in the drain voltage VD of the transistor Tr. As a result, the voltage V1 becomes positive and reinforces the voltage VG to keep the transistor Tr, in a positive feedback manner, fully on. Figures 2a-2c illustrate waveforms useful for explaining the operation of tuned ZPS SMPS 100 of Figure 1A. Similar symbols and numbers in Figures 1A, 1B and 2a-2b indicate similar parts or functions. During an interval tO-t 1 of a given period T of FIG. 2c, the current ID of the conductive transistor Tr of FIG. 1A rises in the form of a ramp. Consequently, a corresponding non-resonant current pulse portion of a current IL1 in the winding L1 rises in a ramp shape and stores magnetic energy in the inductance associated with the winding L1 of the transformer T1. At time t1 of Figure 2c, the voltage VBQ2 of Figure 1A, containing a ramp-shaped lifting portion derived from the voltage across the resistor R12, exceeds a trigger level of the regeneration switch 31 which is determined by the voltage V2 and turn on transistor Q2. Current flows at the base of transistor Q1 and regeneration switch 31 applies a low impedance at the gate electrode of transistor Tr. Consequently, the gate electrode voltage VG of FIG. 2a is reduced to almost zero volts and turns off the transistor Tr of FIG. 1A. When the transistor Tr is turned off, the drain voltage VD of Figure 2b increases and causes the voltage V1 of Figure 1A that is coupled from the winding L3 to be reduced. The load stored in the gate-source capacitance CG maintains a closing mode operation up to time t2 of Figure 2a. When the voltage VG becomes smaller than that required to maintain a sufficient collector current in the transistor Q1 of Fig. 1A, an advance line in the base electrode of the transistor Q2 ceases and, consequently, the closing operation mode in the regeneration switch 31 is disabled. After, the voltage V1, which continues to reduce, causes a negative portion 40 of the voltage VG of Figure 2a to keep the transistor Tr of Figure 1A off. When the transistor Tr is off, the drain voltage VD is increased as shown in Figure 2b. The capacitor C6 of FIG. 1A limits the rate of increase of the voltage VD, so that the transistor Tr is completely non-conductive before the voltage VD increases appreciably above a voltage of zero. In this way, the switching losses and the irradiated switching noise are advantageously reduced. The resonant circuit 21, which includes the capacitor C6 and the winding L1, oscillates, during the interval t1-t3 of FIG. 2b, when the transistor Tr of FIG. 1A is turned off. The capacitor C6 limits the peak level of the voltage VD, Therefore, and advantageously, no braking diode or resistor is needed, so that the efficiency is improved and reduced in noise of the switch.

The reduction in voltage VD, before time t3 of Figure 2b, causes the voltage V1 of Figure 1 to become a positive voltage. At time t3 of Figure 2bm the voltage VD is close to zero volts and is slightly negative, causing the damping diode D6 of Figure 1 to turn on and lock the voltage VD of Figure 2b to approximately zero volts. In this way, the resonant circuit 21 of Figure 1A exhibits a mean cycle of oscillation. After time t3 of Figure 2b, the voltage VG of Figure 2a becomes enormously more positive, due to the aforementioned change in the polarity of the voltage V1 of Figure 1A. Advantageously, the next ignition of the transistor Tr is delayed by a delay time which is determined by the time constant of the resistor R8 and the gate capacitance CG until after time t3 of FIG. 2b when the voltage VD is close to zero volts. . Therefore, minimum ignition losses are incurred and switch noise is reduced. The negative feedback regulation of the B + voltage is achieved by varying the voltage V2 in the C30 filter capacitor. When the base voltage of transistor Q4 which is proportional to voltage B + is greater than the sum of the forward voltage of the base-emitter junction of transistor Q4 and the voltage VREF, the current charges capacitor C30 and increases the base voltage VBQ2 of transistor Q2. Therefore, the threshold level of comparator transistor Q2 is reduced. Consequently, the peak value of the current ID in the transistor Tr and the power supplied to the charging circuit are reduced. On the one hand, when the base voltage of the transistor Q4 is smaller than the sum of the forward voltage of the base-emitter junction of the transistor Q4 and the voltage VREF, the current is zero and the voltage VBQ2 is reduced. Consequently, the peak value of the current ID in the transistor Tr and the power supplied to the charging circuit are reduced. The tuned ZVS SMPS 100 operates in a current mode control, at a current pulse through the current pulse control base. The current pulse of the current ID during the interval t0-t1 of FIG. 2c, flowing in the transistor Tr of FIG. 1A, ends at the time t1 of FIG. 2c, when it reaches the threshold level of the transistor Q2 of the Figure 1 which is established by the error current, le, forming an error signal. The error signal actually controls the peak current of the current pulse of the ID current flowing in the inductance of the winding L1. The voltage B + is coupled to a voltage divider which includes a resistor R36 and a resistor R37. When a portion of the voltage B + that develops in the resistor R37 exceeds an interrupting voltage of a Zener diode D34, which is indicative of the excessive voltage B +, a voltage portion B +, which is developed through a resistor R38 , is coupled to a base of a transistor R39 to turn on transistor Q7. Similarly, when the voltage VFEDB is excessive, the voltage VFEDB is coupled to the base of a transistor Q7 via a resistor R40 and a Zener diode D35 to turn on the transistor Q7. The generation of voltage B + is disabled when transistor Q7 is conductive. The collector transistor Q7 is coupled to the base of transistor Q1 to turn on a latch 31 when transistor Q7 is conductive to disable ZVS SMPS 100 to provide fault protection. The generation of voltage B + is also disabled when a control signal 1H-VCC which is coupled to the base of a transistor Q6 makes transistor Q6 conductive. The collector of transistor Q6 is coupled to the base of transistor Q1 to turn on a latch 31 when transistor Q6 is conductive. The magnitude of voltage B + is controlled through a control signal WIDTH-REF and varies in the -0.29V scale, when the horizontal scan frequency of output stage 101 is 2H and -4V, when the horizontal scan frequency of the output stage 101 is 2.4H. The control signal WIDTH-REF has a component at a vertical velocity to vary the voltage B + in a parabolic form of vertical velocity to provide the East-West distortion correction. The series pass regulator power supply 102 includes a series pass-through power transistor Q8 having a manifold coupled to the terminal T1a of the winding L2 of the transformer T1 via a diode D33. A current limiting resistor R42 couples the input supply voltage RAWB to an emitter of the power transistor Q8. The collector of transistor Q8 is coupled to a filter capacitor C40 and to the anode of diode D33. The voltage developed in the collector of transistor Q8 is coupled to a collector of a transistor Q10 via a collector resistor R43. The collector of transistor Q8 is additionally coupled to a base of transistor Q10 through a voltage divider feedback network that includes a resistor R44 and a resistor R45. A transistor Q11 is coupled to transistor Q10 to form a differential, error amplifier. The base electrode of transistor Q11 is coupled via a resistor R46 to a Zener diode D36 to provide a reference voltage VREF2. A collector electrode of transistor Q11 is coupled via a resistor R47 to a base of a transistor Q12 which is coupled to transistor Q8 in a Darlington configuration. The emitters of the transistors Q10 and Q11 are coupled to a common emitter resistor R48. The power supply of series pass regulator 102 regulates the voltage B +, according to the reference voltage VREF2, in a conventional manner. For example, an increase in the collector voltage of transistor Q8 causes transistor Q11 to conduct less in a manner that reduces the voltage increase in a negative feedback fashion. The control signal WIDTH-REF is coupled to the base of the transistor Q10 via a resistor R41 to vary the voltage B +, produced by the power supply 102, as explained below, in a parabolic form of vertical velocity to provide the East-West correction in the voltage stage 101. A resistor R49 and a resistor R50 are coupled in series with the resistor R42 to form a current path between a terminal, where the input supply voltage, RAWB, is developed and the collector of transistor Q8. A junction terminal 102a between the resistors R49 and R50 is coupled to a base of a protection transistor Q9, fashioning an aspect of the invention. The emitter of transistor Q9 is coupled to voltage RAWB and its collector is coupled to the base of transistor Q12. During normal operation, transistor Q9 is turned off. Assume that as a result of a failure in, for example, output stage 101, an overcurrent condition occurs in transistor Q8 which causes a sufficiently large voltage drop across resistor R42 to turn on transistor Q9. Therefore, a collector current in the conductive transistor Q9 causes the base voltage of the transistor Q8 to increase and a collector voltage of the transistor Q8 to decrease. The reduction in the collector voltage of transistor Q8 is applied in a positive feedback form to the base of transistor Q9 through resistor R50 to cause an increase in collector current of transistor Q9. Through a regeneration action, the collector voltage of transistor Q8 is further reduced. The result is that transistor Q8 is turned off and stays off through a closing operation. Therefore, an overcurrent protection is obtained. The ZVS SMPS 100 is enabled through the control signal 1H-VCC. When the ZVS SMPS 100 is enabled, the magnitude of the voltage B + that is produced at the cathode of the diode D33 exceeds the anode voltage of the diode D33 or the collector voltage of the transistor Q8. Thus, the diode D33 disconnects the power supply 102 from the terminal T1a of the winding L2 and no power is supplied to the output stage 101 of the power supply 102. To carry out a further aspect of the invention, when the scanning frequency horizontal of the current i and in the output stage 101 is 1H, the ZVS SMPS 10 is disabled by the control signal 1H-VCC; therefore, the magnitude of the voltage B + that is produced at the cathode of the diode D33 is smaller than the anode voltage of the diode D33. Consequently, the power supply 102 is coupled to the terminal T1a of the winding L2 to energize the output stage 101 through the power transistor Q8. The ZVS SMPS 100 is enabled and the power transistor Tr applies power to the output stage 101, when the horizontal scan frequency of the output stage 101 is between 2H and 2.4H. The ZVS SMPS 100 supplies the energy when the deviating frequency is at 2nH which is a relatively narrow frequency scale. While, the power supply of serial step regulator 102 supplies the energy when the diverting frequency is at 1H. The zero voltage switching and its associated advantages could have been compromised if the scale of voltages that the ZVS SMPS 100 requires to regulate has been wide. Therefore, advantageously, by using power supply 102 to energize step 101 when the scanning frequency is 1H, the ZVS SMPS 100 operates on a substantially narrower frequency scale than that required without the power supply of the regulator. series step 102. Consequently, the zero voltage switching aspect is not compromised. Advantageously, since, during operation, only one of the power transistors Tr and Q8 selectively provides power to the output stage 101, both share a common thermal collector arrangement HS. Advantageously, the removal capacity of the dissipated energy of the HS thermal collector arrangement does not need to exceed the requirement that only that energy transistor dissipates the energy in a greater manner. Figure 1B illustrates a control circuit 200 of the arrangement of Figure 1A. Similar symbols and numbers in Figures 1A, 1B and 2a-2c indicate similar parts or functions. In Figure 1B, the control circuit 200 includes a conventional phase closure loop (PLL) 203 having a phase detector 204 coupled to a low pass filter 205. The low pass filter 205 is coupled to an input of frequency control 206 of a controlled voltage oscillator (VCO) 207. The VCO 207 generates an LLC signal at a high multitude of a horizontal velocity synchronization signal HORZ-SYNC. The LLC signal is coupled to a frequency divider, not shown, which is included in a diverter processor 202 formed by an integrated circuit TDA 9151. The processor 202 includes a frequency divider, not shown, having a frequency division factor. selectable controlled by a PRESCALER signal. When in operation at the 1H speed that is required, the PRESCALER signal is at a first state. On the other hand, when 2H-2.4H is required in the operation, the PRESCALER signal is in a second state and the frequency division factor is half of that when 1 H operation is required in the operation. A divided OFCS frequency signal at horizontal speed it is coupled to an input of the phase detector 204. The horizontal speed synchronization signal HORZ-SYNC is coupled to a second input of the phase detector 204. The phase detector 204 controls the phase and the signal frequency OFCS, so that they are equal to the phase and frequency of the HORZ-SYNC signal, respectively. The diverter processor 202 includes a conventional phase control loop, not shown, that generates the signal 107a. The signal phase 107a is automatically set in the processor 202 according to a FLY back pulse signal developed in the winding TOW2 of Figure 1A which will be synchronized to the phase of the HORZ-SYNC signal of Figure 1B. A microprocessor 208 generates on an I2C bus a control signal 208a which is coupled to the diverter processor 202 to selectively enable and disable the control signal 107a. When enabled, the signal 107a produces a periodic switching operation in the output stage 101 of FIG. 1A.

When disabled, the signal 107a avoids the periodic switching operation in step 101. The microprocessor 208 responds to a word signal 209a generated in a data signal frequency converter 209. The signal 209a has a numerical value that is indicative of the frequency of the HORZ-SYNC synchronization signal. The converter 209 includes, for example, a counter that counts the number of clock pulses, during a given period of the HORZ-SYNC signal, and generates the word signal 209a according to the number of clock pulses occurring in the clock. given period. The microprocessor 208 also generates on the busbar I2C a control word signal 208b which is coupled to a digital to analog converter (D / A) 201 and a control word signal 208c which is coupled to a data register 211. The signals 208b and 208c are determined according to the signal 209c. Alternatively, the value of the signals 208b and 208c may be determined by a signal 109b that is provided by a keyboard, not shown. The D / A converter 201 generates, in accordance with the word signal 208b, a similar control signal VCO-FREQ which is coupled to the VCO 207 to control the free-run frequency of the VCO 207 at the different scanning speeds. The D / A converter 201 also generates, according to the data signal 208b, a width alignment signal WIDTH-ALIGN. The WIDTH-ALIGN signal is summed in an adder 210 with the vertical velocity parabola signal EW-GEOMETRY-WIDTH produced in the deviator processor 202, in accordance with the vertical synchronization signal VERT-SYNC. The adder 210 generates a WIDTH-REF parabola signal that is coupled to each of the power supplies 102 and 100. The WIDTH-REF signal has a direct current component to control a direct current component of the supply voltage B + for control the width and a vertical velocity parabola component to provide the East-West distortion correction. The register 211 generates, according to the word signal 208c, a control signal SCSEL that controls the selection of switched capacitors S 106 of FIG. 1A. The register 211 further generates a control signal 1H-VCC according to the signal 208c to disable the ZVS SMPS 100, when the required scanning frequency is 1H and to enable the ZVS SMPS 100, when the required scanning frequency is equal or greater than 2H. The register 211 also generates the PRESCALER signal in the first state, when the required scanning frequency is 1H and in the second state, when the required scanning frequency is 2H-2-4H. Accordingly, the diverter processor 202 generates the switch control signal 107a at the horizontal scan frequency selected to control the horizontal driver 103 of Figure 1A. During a first actuation or ignition step, the switch control signal 107a is disabled by the signal 208a of the microprocessor 208, so that the output transistor 104 of Figure 1A is continuously maintained non-conductive. Also, the data register 211 of Figure 1B generates the control signal 1H-VCC at a level which causes the transistor Q6 of Figure 1A to turn on and disable the ZVS SMPS 100. In this way, the output stage 101 is energized from the power supply 102 that generates the lower supply voltage B +. In a second step of the ignition sequence, the control signal SCSEL is determined by selecting the S-shaped capacitor 106 of Figure 1A. Also, the signals PRESCALER, VCO-FREQ and WIDTH-ALIGN are determined. The signals PRESCALER and VCO-FREQ adjust the frequency of the control signal 107a, when the signal 107a is enabled. In a third step that follows, the signal 208a enables the control signal 107a of the processor 202 to provide the periodic switching operation in the transistor 104 of Figure 1A at the required frequency. If the upper 2nH operation mode is selectedthen, in a fourth step that follows, the microprocessor 208 of FIG. 1B will cause the register 211 to generate, after a sufficiently long start delay, the control signal 1H-VCC at a level which causes the transistor Q6 of Figure 1A turns off. Therefore, the upper supply voltage B + is generated in the ZVS SMPS 100. The delay is proclaimed when the ZVS SMPS 100 is enabled only after the horizontal scanning output stage 101 has been run for a sufficiently long interval and reaches the stable state operation with the lower supply voltage B +. During the mode of operation, the procedure for changing the scanning speed from mode 1H to mode 2nH, when initiated by the user, for example, includes a first step wherein the signal 107a is disabled by the operation of the signal 208a of the microprocessor 208, and transistor 104 of Figure 1A remains non-conductive. Then, in a second step, the control signals SCSEL, PRESCALER, VCO-FREQ and WIDTH-ALIGN are determined. The operation of the PRESCALER signal is to increase the frequency of the signal 107a, when the signal 107a is enabled, at the speed of 2nH. Then, in a third step, the signal 208a enables the control signal 107a to provide the periodic switching operation in the transistor 104 of Figure 1A at the speed of 2nH. Then, in the fourth and last step, the ZVS SMPS 100 signal is enabled via the 1H-VCC signal only after the horizontal scanning output stage 101 has been run for a sufficiently long interval and reaches a stable state operation with the lower supply voltage B +. The procedure to change the scanning speed from 2nH mode to 1H mode is similar to changing it from mode 1H to 2nH except that, in the second step, the control signals correspond to the operation at the speed of 1H instead of the operation at the speed of 2nH. Also, the fourth step is not realized. The power interruption is implemented by disabling the ZVS SMPS 100 signal before the horizontal scanning frequency can be reduced. Advantageously, each of the mode change procedures avoids energizing the horizontal scanning stage 101 with the highest voltage B +, when the switching operation is at the speed of 1H. Also, at each step where the signal 107a is enabled, a moderate start aspect is implemented by reaching the final duty cycle value of the signal 107a in a gradual manner, over several cycles. Thus, advantageously, the excessive voltage in the switching transistor 104 of the horizontal output stage 101 is reduced to have an improved operational safety.

Claims (13)

1. - A display diverting apparatus capable of selectively operating at a diverting frequency selects from a frequency scale, comprising: a source of a synchronization signal at a frequency indicative of said selected frequency; a diverter circuit output stage (101) that responds to the synchronization signal to generate a diverting current (iy) at said diverting frequency; a first power supply (100) including a first transistor (Tr) for generating a first supply voltage through the operation of the first energy transistor when a first diverter frequency is selected; a second power supply (102) including a second power transistor (Q8, Q12) for generating a second supply voltage through the operation of said second power transistor when a second diverter frequency is selected; and a source of a signal (HORZ-SYNC) indicative of said frequency of the synchronization signal to generate a first control signal (1H-VCC) that is coupled to one of the first and second power supplies to select, in accordance with this, the first voltage supply for energizing the deviator circuit output stage, when said first deviation frequency is selected, and said second supply voltage, when the second deviation frequency is selected, so that when the first supply voltage energizes the output stage, the second power transistor is outside a supply current path of said output stage, and, when the second supply voltage energizes the output stage, the first energy transistor is outside the output stage. supply current path of the output stage (101).

2. A display diverting apparatus according to claim 1, wherein each of the first and second supply voltages is selectively coupled to a common supply terminal (B +) of the deviator circuit output stage (FIG. 101).

3. A display diverting apparatus according to claim 2, wherein said second supply voltage is coupled to the common supply terminal through a diode (D33) that is deflected forward to couple the second transistor of energy (Q8, Q12) to said compound step (101), when said second voltage supply is selected, and is diverted back to decouple the second transistor from the output stage, when the first supply voltage is selected.

4. A visual display diverting apparatus according to claim 1, further comprising a source of a second control signal (WIDTH-REF) coupled to the power supply to vary a magnitude of the first voltage supply, in accordance with the frequency of said diverting current (iy).

5. A display diverting apparatus according to claim 1, wherein said first power supply comprises a power supply of zero voltage switching switch (100).

6. A display diverting apparatus according to claim 5, wherein said second power supply comprises a power supply of step regulator in series (102).

7. A display diverting apparatus according to claim 1, wherein, during an ignition interval, one of the first or second supply voltages having a lower voltage is selected to energize said deflector circuit output stage. without considering the frequency selected.

8. A display diverting apparatus according to claim 1, further comprising an oscillator (207) for generating a second control signal (LLC) that is coupled to a switching transistor (104) of said output stage of diverter circuit (101) to control a switching operation at the selected frequency, wherein, during a power reduction interval, said first control signal selects the power supply (102) that generates a lower voltage to energize the deviator circuit output stage and wherein, during said derating interval. energy, a reduction in the selected frequency is avoided.

9. A display diverting apparatus according to claim 1, further comprising an oscillator (207) for generating a second control signal (LLC) that is coupled to a switching transistor (104) of said output stage of diverter circuit (101) for controlling a switching operation at the selected frequency, wherein said first diverting frequency is greater than the second diverting frequency, and wherein, when a reduction in the diverting frequency is required from the first to the second frequency, said first control signal selects the second supply voltage to energize the output stage, during a transition interval, before the frequency reduction of said oscillator.

10. A display diverting apparatus according to claim 1, further comprising an oscillator (207) for generating a second control signal (LLC) that is coupled to a switching transistor (104) of the output stage of diverter circuit (101) for controlling a switching operation at the selected frequency, wherein the first diverting frequency is greater than the second diverting frequency, wherein, when an increase in the diverting frequency is required from the second to the first frequency, said increase in the diverting frequency occurs, during a transition interval, and before the selection of the first supply voltage to energize said output stage.

11. - A display diverting apparatus according to claim 1, wherein said first (Tr) and second power transistors (Q8, Q12) share a common thermal collector arrangement that removes the heat generated only in one of the transistors in any given moment.

12. A display diverting apparatus according to claim 1, wherein said first control signal source comprises a frequency detector (209) that responds to the synchronization signal.

13. A display diverting apparatus capable of selectively operating at a selected deviation frequency of a frequency scale, comprising: a source (HORZ-SYNC) of a synchronization signal at a frequency indicative of the selected frequency; a diverter circuit output stage (101) that responds to the synchronization signal to generate a diverting current (iy) at the selected diverter frequency; a first power supply (100) for generating a first supply voltage when the first diverting frequency is selected; a second power supply (102) for generating a second supply voltage when a second diverter frequency is selected; and a source (209) of a signal indicative of a frequency of the synchronization signal to generate a first control signal (1H-VCC) that is coupled to one of the first and second power supplies to select, in accordance with the same, the first supply voltage to energize the deflector circuit output stage, when the first diverter frequency is selected, and the second supply voltage, when the second diverter frequency is selected, so that during a firing interval, one of the first and second supply voltages having a lower voltage is selected to energize said bypass circuit output stage without considering the selected frequency.