JPH0591359A - Switch driving circuit - Google Patents

Abstract

PURPOSE:To prevent the sexy distortion from being generated. CONSTITUTION:A waveform shaping circuit 120 waveform-shapes a flyback pulse corresponding to a horizontal deflection cycle. A differentiating circuit 121 differentiates a horizontal driving pulse. From the output of the waveform shaping circuit 120 and the differentiating circuit 121, a charging discharging control signal generating circuit 122 (comparator 91) generates a charging discharging control signal. The charging discharging control signal controls the charging discharging of a charging discharging circuit 123. The saw tooth wave generated by the charging discharging circuit 123, after it is clamped by a clamping circuit 127, is supplied to a trapezoidal saw tooth wave signal generating circuit 128. The trapezoidal saw tooth wave signal, after the inclination is adjusted in correspondence to an ABL voltage by an inclination adjusting circuit 129, is inputted to a comparing circuit 124. Then, the signal is changed at the vertical deflection cycle, compared with a reference signal level phase- compensated by a phase compensating circuit 130 and a PWM signal as a switch driving signal is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch driving circuit suitable for driving a switching element of a deflection current generating circuit in, for example, a television receiver or a monitor device.

[0002]

2. Description of the Related Art FIG. 21 shows a conventional configuration example of a horizontal deflection circuit and a circuit in the vicinity thereof in a television receiver. A power supply 3 is connected to the horizontal deflection circuit 1 via a primary coil 2 a of a flyback transformer 2. A rectifying / smoothing circuit including a diode 4 and a capacitor 5 is connected to the secondary winding 2b of the transformer 2. The horizontal deflection current output from the horizontal deflection circuit 1 is the CR having the screen 6a.
It is adapted to be supplied to the deflection yoke 7 of T6.

FIG. 22 shows the internal structure of the horizontal deflection circuit 1. In this example, the horizontal deflection circuit 1 has N
A parallel circuit including a PN transistor 22, a diode 23, and a capacitor 24 is connected in parallel with a series circuit of the deflection yoke 7 and the capacitor 25. Also, in this example, the transformer 2 and the secondary coil 2 are
c is provided, and its output is rectified by the diode 21 and output.

Next, the operation will be described. Power supply 3
The DC voltage output from the primary coil 2a of the transformer 2
Is supplied to the collector of the NPN transistor 22 via. The NPN transistor 22 is turned on / off by supplying a signal corresponding to the horizontal deflection period to its base. As a result, a flyback pulse (retrace pulse) Vcp as shown in FIG. 23B is generated at the collector of the NPN transistor 22.

Capacitors 24 and 25 and deflection yoke 7
Constitutes a resonance circuit, and performs resonance operation corresponding to the switching operation of the NPN transistor 22. As a result, as shown in FIG. 23A, a so-called sawtooth wave deflection current I ₇ , which linearly increases in the trace section and linearly decreases in the retrace section, flows in the deflection yoke ₇ . As a result, the electron beam is scanned (deflected) in the horizontal direction on the screen 6a of the CRT 6.

The flyback pulse voltage Vcp is
The voltage is boosted by the secondary coil 2c of the flyback transformer 2 and rectified by the diode 21 to generate the high voltage Hv. This high voltage Hv is supplied to the anode of the CRT 6. Further, the voltage output from the secondary coil 2b is rectified by the diode 4 and smoothed by the capacitor 5 to become the DC voltage Vc. This voltage Vc is used as a focus voltage of the CRT 6, a heater voltage, and the like.

By the way, as shown in FIG. 24 (b), the distance from the electron gun 6b to the screen 6a is shortest at the center of the screen 6a and longest at the upper end or the lower end of the screen 6a. As a result, so-called horizontal pins (PIN) are generated as shown in FIG. If this horizontal pin is left as it is, the displayed image will be distorted. Therefore, a circuit for correcting the horizontal pin is usually added to the horizontal deflection circuit.

FIG. 25 shows the principle of the horizontal deflection circuit disclosed in Japanese Patent Publication No. 57-39102. That is, in this example, the DC voltage output from the power supply 31 passes through the coil 32, the switch 33, and the capacitor 2
4 and the horizontal deflection coil 7 and the capacitor 25 are supplied to a parallel circuit composed of a series circuit. The power supply 31 and the coil 32 correspond to the power supply 3 and the primary winding 2a of the flyback transformer 2 in FIG. The switch 33 corresponds to a parallel circuit including the NPN transistor 22 and the diode 23.

In this example, a switch 34, a capacitor 24, a capacitor 35, and a coil 36 and a capacitor 37 are provided in a parallel circuit (first parallel circuit) including a series circuit of the switch 33, the capacitor 24, the horizontal deflection coil 7 and the capacitor 25. Parallel circuit of a series circuit (second parallel circuit)
Are connected. Then, a series circuit including a coil 38 and a power source 39 is connected in parallel to the second parallel circuit.

That is, the horizontal deflection circuit has a structure in which the first parallel circuit is connected to the second parallel circuit having the same structure as the first parallel circuit.

To correct the horizontal pin, as shown in FIG. 26 (a), a retrace pulse (terminal voltage V _{24 of the} capacitor ₂₄ ) applied to the horizontal deflection coil 7 in accordance with the vertical deflection cycle is It is necessary to adjust so that the level at the substantially central portion (even on the screen) is higher than the levels at the left and right end portions (upper and lower end portions on the screen). The level of the retrace pulse obtained by adding this voltage V ₂₄ and the terminal voltage V ₃₅ of the capacitor 35 is the power supply 31.
Since it is defined by the width of the retrace pulse, it becomes constant as shown in FIG. Therefore, the voltage V
_As shown in FIG. 26 (b), the value of ₃₅ becomes smaller at the central portion (central portion on the screen) corresponding to the vertical deflection period, and becomes smaller at the left and right end portions (upper and lower end portions on the screen). The terminal voltage V ₂₄ is changed by increasing the voltage
It is possible to adjust the level at the substantially central portion (the central portion on the screen) to be higher than the levels at the left and right end portions (upper and lower end portions on the screen).

Therefore, in this example, the switch 34 is switched at the same timing as the switch 33 to generate a retrace pulse at the connection point between the capacitor 35 and the coil 38, and the voltage output from the power supply 39 is changed as shown in FIG. As shown in (b), the value is changed such that the value becomes smaller at the central portion (central portion on the screen) and increases at the left and right end portions (upper and lower end portions on the screen) corresponding to the vertical deflection cycle. As a result, the voltage V ₂₄ becomes
As shown in FIG. 26 (a), the level at the substantially central portion (central portion also on the screen) changes so as to be higher than the levels at the left and right end portions (upper and lower end portions on the screen), The horizontal pin will be corrected.

In addition to this, as a method for correcting the horizontal pin,
The power supply modulation method and the PCT method are known. In the power supply modulation method, for example, in FIG. 22, the voltage of the power supply 3 is modulated in the vertical deflection cycle. The PCT method is shown in FIG.
2, a secondary winding of a transformer is connected in series to the horizontal deflection coil 7, and a vertical deflection current is passed through the primary winding.

However, in any of these methods,
Since the voltage Vcp is modulated in the vertical deflection cycle, various voltages taken out from the transformer 2 are also modulated in the vertical deflection cycle, and in a so-called separate type circuit in which a horizontal deflection circuit and a high voltage generation circuit are separately provided. Although it can be applied, it has a problem that it cannot be used in a so-called conventional type circuit in which both are integrated. In that respect, the method shown in FIG.
Even when 2 is configured as the primary winding of the transformer, various voltages taken out from the secondary winding are not modulated in the vertical deflection cycle, and are applicable not only to the separate type but also to the conventional type horizontal deflection circuit. Can be used.

[0015]

However, in the circuit having the configuration shown in FIG. 25, in addition to supplying current to the switch 34, the capacitor 35, and the second parallel circuit composed of the series circuit of the coil 36 and the capacitor 37, the coil 38 is used. And power 3
Since it is necessary to supply current to the serial circuit of 9 as well, there is a problem that power consumption increases.

The present invention has been made in view of such a situation, and in the case where the switching element is driven to generate the deflection current so that the power consumption can be further reduced in the deflection current generating circuit. , To prevent the occurrence of sexy distortion.

[0017]

A switch drive circuit of the present invention is a switch drive circuit for driving a switching element that switches in accordance with a horizontal deflection period and a vertical deflection period, and a flyback pulse corresponding to the horizontal deflection period. A waveform shaping circuit 120 for shaping the waveform, a differentiating circuit 121 for differentiating the horizontal drive pulse corresponding to the horizontal deflection period,
A charge / discharge control signal generation circuit 122 for generating a charge / discharge control signal from the outputs of the waveform shaping circuit 120 and the differentiation circuit 121;
Charging / discharging circuit 123 for charging / discharging in response to a charging / discharging control signal
And a clamp circuit 127 that clamps the output of the charge / discharge circuit to a predetermined level, and a trapezoidal sawtooth wave signal generation circuit 1 that generates a trapezoidal sawtooth wave signal from the output of the clamp circuit 127.
28, a comparison circuit 124 for comparing the trapezoidal sawtooth wave signal generated by the trapezoidal sawtooth wave signal generation circuit 128 with a reference level corresponding to the vertical deflection period, and phase compensation of the reference level supplied to the comparison circuit 124. Phase compensation circuit 130
And is provided.

[0018]

In the switch drive circuit having the above structure, the waveform shaping circuit 120 shapes the flyback pulse, and the differentiating circuit 121 differentiates the horizontal drive pulse. The charge / discharge control signal generation circuit 122 is the waveform shaping circuit 12
A charge / discharge control signal is generated from 0 and the output of the differentiating circuit 121 to control the charge / discharge operation of the charge / discharge circuit 123. The output of the charge / discharge circuit 123 is clamped to a predetermined level by the clamp circuit 127. Trapezoidal sawtooth wave signal generation circuit 12
8 generates a trapezoidal sawtooth wave signal from the output of the clamp circuit 127. This trapezoidal sawtooth wave signal is input to the comparison circuit 124 and compared with the reference level. The phase of the reference level is compensated by the phase compensation circuit 130. The flyback pulse corresponds to the horizontal deflection cycle, and the reference level corresponds to the vertical deflection cycle. Therefore, the occurrence of sexy distortion is prevented.

[0019]

FIG. 12 is a circuit diagram showing the configuration of an embodiment of a deflection current generating circuit to which the switch driving circuit of the present invention is applied. Parts corresponding to those in FIGS. 21, 22 and 25 are shown in FIG. The same reference numerals are attached. In this embodiment, a switch 33, a capacitor 24, a parallel circuit composed of a series circuit of the horizontal deflection coil 7 and the capacitor 25,
A parallel circuit of the switch 73 and the capacitor 74 is connected in series. The switch 33 is controlled by the control circuit 71 in accordance with the horizontal deflection cycle, and the switch 73 is controlled by the control circuit 72 in accordance with the horizontal deflection cycle and the vertical deflection cycle. ing.

Next, the operation will be described with reference to the timing chart of FIG. The switch 33 is a control circuit 71
Is turned on during the horizontal deflection trace section and turned off during the retrace section (FIG. 13B). The sawtooth current I ₃₂ (FIG. 13A) flowing through the coil 32 is
When the switch 33 is on, it flows through the switch 33,
When the switch 33 is off, it flows through the capacitor 24. The switch 73 is controlled by the control circuit 72, and is turned off for a predetermined time in the retrace section in which the switch 33 is off (FIG. 13 (e)). Current I ₃₂ is switch 3
When switches 3 and 73 are on, these switches 33 and 73
When both switches 33 and 73 are off, they flow through capacitors 24 and 74. When the switch 33 is off and the switch 73 is on, the capacitor 24 and the switch 73 flow. When the switch 33 is off,
A sawtooth wave current I ₇ flows through a resonance circuit composed of the horizontal deflection coil 7 and the capacitors 25 and 24.

The capacity of the capacitor 24 is the same as that of the capacitor 74.
It is set to a value smaller than the capacity of. Therefore, the length (time) Tr of the retrace period is substantially equal to that of the capacitor 24.
And 25, and the inductance of the horizontal deflection coil 7, even if the capacitor 74 is connected,
It takes almost the same time as when not connecting. Coil 3
It is known that the voltage Vcp between the connection point of 2 and the horizontal deflection coil 7 and the ground potential is obtained by the following equation. Vcp = E (1+ (π / 2) (Tt / Tr)) (1)

This voltage Vcp is equal to the sum of the terminal voltage V ₂₄ of the capacitor ₂₄ and the terminal voltage V ₇₄ of the capacitor 74. That is, the following equation is established. Vcp = V ₂₄ + V ₇₄ (2)

The energy for deflection is stored in the condenser 7
When (4) is not connected, (1/2) C ₂₄ Vcp ² is obtained, but when the capacitor 74 is connected as shown in FIG. 12, it becomes (1/2) C ₂₄ V ₂₄ ² . Since V ₂₄ is smaller than Vcp, capacitor 74
The deflection current I ₇ is reduced in the case where the connection is made as compared with the case where the connection is not made. Therefore, when the voltage V ₇₄ is adjusted by adjusting the period during which the switch 73 is off (the period during which the switch 73 is on), the voltage V ₂₄ can be consequently adjusted, and further the deflection current I ₇ can be adjusted. As a result, it becomes possible to adjust the raster size. Further, the left and right pins can be corrected by adjusting the period during which the switch 73 is turned off in the vertical deflection cycle.

This will be further described with reference to FIG. 13. In the lithographic section in which the switch 33 is off, the capacitor 24 has a combined current I _{24 of the} current I ₃₂ and the current I _7.
(FIG. 13C) flows. Since the currents I ₃₂ and I ₇ are both sawtooth wave currents, the current I ₂₄ is as shown in FIG. For example, if the switch 73 is turned on and off at exactly the same timing as the switch 33, the current I
_{Since 32} flows to ground through switch 73 or capacitor 74, current I ₇₄ is transferred to switch 33 (or 7
3) becomes equal to the current flowing through the capacitor 24 in the off period.

As shown in FIG. 13E, the switch 73
When the OFF timing of the switch 33 is delayed from the OFF timing of the switch 33 (FIG. 13B), the current I ₃₂ flows through the switch 73 while the switch 33 is OFF and the switch 73 is ON. In a section in which both 73 are off, the capacitors 24 and 74 flow. Therefore, the current I ₇₄ has a waveform shown by the solid line in FIG. 13F (a waveform obtained by cutting out the current I ₃₂ ). That is, by adjusting the timing of turning off the switch 73,
It is possible to change and adjust the section for cutting out the current I ₃₂ ,
The current I ₇₄ has a similar current waveform in which the width and the height change at the same rate as the current I ₃₂ . Therefore, the capacitor 24
The voltages V ₂₄ and V ₇₄ (Figs. 13 (d) and 13 (g)) generated at and 74 have different resonance frequencies, but have substantially similar voltage waveforms. As a result, if the OFF timing of the switch 73 is adjusted in accordance with the vertical deflection period, the current I ₇₄ flowing through the capacitor 74, and hence the voltage V ₇₄ generated there, changes, and as a result, the capacitor 24 changes. The generated voltage V ₂₄ changes (FIGS. 13D to 13G).

In this case, since the coil 38 and the power supply 39 shown in FIG. 25 are omitted, it is not necessary to supply energy from the coil 32 to the coil 38 and the energy consumed is reduced accordingly. be able to.

FIG. 14 shows the configuration of the second embodiment of the deflection current generating circuit to which the switch driving circuit of the present invention is applied. In this embodiment, the switch 33 in the embodiment of FIG. 12 is the NPN transistor 22 and the diode 2.
3 is a parallel circuit, and the switch 73 is FET4
1 and a diode 42 are connected in parallel.
Other configurations are similar to those in FIG.

FIG. 15 is a timing chart showing the operation of the embodiment shown in FIG. As shown in FIG.
When the FET 41 is turned off as shown in FIG. 7C while the NPN transistor 22 is off, the terminal voltage V ₇₄ of the capacitor 74 becomes as shown in FIG. The retrace pulse voltage Vcp at the connection point between the coil 32 and the horizontal deflection yoke 7 is, as shown in FIG. 15B, a terminal voltage V _{74 of the} capacitor 74 shown in FIG. 15D and a capacitor shown in FIG. It is the sum of ₂₄ terminal voltages V ₂₄ . Therefore, the frequency (width) and height of the pulse voltage V ₇₄ generated at both ends of the capacitor 74 can be adjusted by adjusting the timing when the FET 41 is turned off in accordance with the vertical deflection period. Here, increasing the frequency means narrowing the width of the pulse shown in FIG. 15D, and lowering the frequency means widening the pulse. When the width of the pulse is narrow, the height of the pulse is low, and when the width is wide, the height of the pulse is high. As a result, the voltage V
The voltage V _{24 obtained} by subtracting the voltage V ₇₄ from cp (constant) is shown in FIG.
It will change as shown in (e).

Although FIG. 15 shows only the off period of the NPN transistor 22 and the FET 41,
The turn-on timings of the diodes 23 and 42 are the same when the voltage Vcp becomes 0 or the voltage V ₇₄ becomes 0, respectively. Therefore, when the NPN transistor 22 and the diode 23 are regarded as one switch 33, and the FET 41 and the diode 42 are regarded as one switch 73, the operation is the same as in the case of FIG.

Coil 32 shown in FIGS. 12 and 14.
Can be configured as a primary coil of the flyback transformer 2 as shown in FIG. In this case, 51 and 54 are provided as secondary coils. Secondary coil 5
The output of 1 is rectified by the diode 52, divided by the resistor 53, and output as the focus voltage. The outputs of the secondary coil 54 are output as pulses having mutually opposite polarities.

FIG. 17 shows a third embodiment of the deflection current generating circuit. In this embodiment, the emitter of the NPN transistor 22 in the embodiment shown in FIG. 14 is grounded. Other configurations are similar to those in FIG. Even in the case of such a configuration, the same operation as in the case shown in FIG. 14 can be executed.

By the way, in the embodiment shown in FIGS. 12, 14 and 17, when the DC component of the current I ₃₂ flowing through the coil 32 fluctuates as shown in FIG. In response to the switching operation of the switch 73 shown in (), a current I ₇₄ flows through the capacitor 74 as shown in FIG. That is, at this time, in the state where the DC component is superimposed (the state shown on the right side in FIG. 18),
The current I ₇₄ changes non-linearly, and the terminal voltage V ₇₄ of the capacitor 74 changes as shown in FIG. 18 (d). This means that when the current I ₃₂ flowing through the coil 32 changes, the raster size also changes. Therefore, although it can be applied to a so-called separate type circuit in which the horizontal deflection circuit and the high voltage generating circuit are separately provided, it is not suitable for a so-called conventional type circuit in which the both are integrated.

FIG. 19 shows an embodiment of a deflection current generating circuit which can be used also in a conventional type circuit from such a viewpoint. In this embodiment, the transformer 2 is composed of a primary coil including a coil 32 and a secondary coil 61. The secondary coil 61 is connected to the connection point between the capacitor 74 and the capacitor 25 via the series circuit of the coil 63 and the capacitor 62. Other structures are the same as those in the embodiment shown in FIGS. 12 and 14. That is, in this embodiment, the horizontal deflection coil 7
A secondary coil 61, a coil 63, and a capacitor 62 with respect to the main resonance circuit including the capacitors 25 and 24.
Also, a sub-resonant circuit including a capacitor 74 is connected.

With this structure, current flows through the path of the capacitor 74, the capacitor 62, the coil 63, and the secondary coil 61 of the transformer 2 in the first half of the retrace section, and the reverse path in the latter half of the retrace section. A current I ₆₃ flows through the coil 63.

The frequency of the trace interval in the main resonant circuit is defined by the capacitance C ₂₅ of the inductance L ₇ and capacitor 25 of the horizontal deflection coil 7, in retrace interval L ₇ and C _25, and the electrostatic capacitor 24 It is defined by the capacitance C ₂₄ . Further, in the sub-resonance circuit, the capacitance of the capacitor 62 is C in the trace section.
₆₂ and the inductance M _{63 of the} coil 63 (described later), and in the retrace section, M ₆₃ and C ₆₂ and the capacitance C ₇₄ of the capacitor 74 (Table 1
reference).

[Table 1]

In the main resonance circuit and the sub-resonance circuit, the frequency f _T in the trace section needs to be set to a value sufficiently smaller than the frequency f _{R in the} retrace section. That is, the trace section needs to be set to a time sufficiently longer than the retrace section. To achieve this, C ₆₂
Is set to a value sufficiently larger than C ₇₄ .

That is, the frequencies f _T and f _R are expressed by the following equations. f _T = 1 / (2π (M ₆₃ C ₆₂ ) ^1/2 ) ・ ・ ・ ・ ・ (3) f _R = 1 / (2π (M ₆₃ C ₀ ) ^1/2 ) ・ ・ ・ ・ ・ (4) Here, C ₀ is a series combined capacitance of the capacitors 62 and 74, and is represented by the following equation. C ₀ = C ₆₂ C ₇₄ / (C ₆₂ + C ₇₄ ) ... (5) Further, M ₆₃ is not the original inductance L ₆₃ of the coil ₆₃ , but is defined according to the voltage applied across the coil 63. Is the inductance.

That is, as shown in FIG. 20, the terminal voltage V ₇₄ of the capacitor ₇₄ and the output voltage V ₆₁ of the secondary coil 61 of the transformer 2 are applied to one terminal and the other terminal of the coil 63. As a result, the inductance M ₆₃ that contributes to the resonant operation of the sub-resonant circuit is expressed by the following equation. M ₆₃ = L ₆₃ V ₇₄ / (V ₇₄ + V ₆₁ ) ... (6)

The virtual ground point of the coil 63 is the voltage V _{74 at} both ends.
And V ₆₁ corresponding to the voltage value of V ₆₁ .

By the way, since f _T is sufficiently smaller than f _R ,
The following equation holds. 1 / (2π (M ₆₃ C ₆₂ ) ^1/2 ) << 1 / (2π (M ₆₃ C ₀ ) ^1/2 ) ... (7) From the above equation, the following equation is obtained. M ₆₃ C ₆₂ >> M ₆₃ C ₀ (8) Rearranging the above equation gives the following. C ₆₂ >> C ₀ (9) Here, if C ₆₂ >> C ₇₄ , the value of C ₀ is almost C _74.
The above equation is satisfied, as defined by.

Further, since the frequency is determined in accordance with the product of M ₆₃ (L ₆₃ ) and C ₇₄ , M ₆₃ (L ₆₃ ) needs to be set to a value sufficiently large for C ₇₄ . ..

Since the coil 61 applies a predetermined bias to the capacitor 74 via the coil 63 and the capacitor 62, the transformer 2 is greatly affected by the current flowing from the coil 63 to the secondary coil 61 of the transformer 2. It is necessary to prevent such things from being received. So 2
The inductance L ₆₁ of the next coil 61 needs to be set to a value sufficiently larger than the inductance L _{63 of the} coil 63.

As described above, the secondary coil 6 of the transformer 2
When the current I ₆₃ is supplied as a bias from 1 to the capacitor 74 through the coil 63 and the capacitor 62, a combined current of I ₃₂ and I ₆₃ flows in the capacitor 74 in a steady state. Therefore, if the current I ₆₃ is set to a value that is sufficiently larger than the current I ₃₂ , even if the current I ₃₂ changes in response to the change in the high voltage applied on the secondary side of the transformer 2, the current I ₃₂ flows to the capacitor 74. The amount of change in current can be relatively small. Therefore, a flyback transformer can be used as the transformer 2, and it can be applied to a so-called conventional type circuit.

The capacitor 62 in FIG. 19 may be connected between the capacitor 25 and the capacitor 74 so as to be shared by the main resonance circuit and the sub resonance circuit. In addition, the emitter of the NPN transistor 22 is shown in FIG.
It can also be grounded as in 7.

In the above embodiment, the switch 33 is composed of the NPN transistor 22 and the diode 23 and the switch 73 is composed of the FET 41 and the diode 42. However, the switch 33 is composed of the FET and the diode. The switch 73 can also be composed of a transistor and a diode. Further, both the switches 33 and 73 can be configured by transistors and diodes, or can be configured by FETs and diodes. Further, when the FET is used, its parasitic diode can be used to omit the external diode. Generally, using an FET can simplify the drive and increase the switching speed, as compared with the case where a transistor is used.

The switch 73 in each of the above-described embodiments
The control circuit 72 as a switch drive circuit for driving the (FET 41) can be configured as shown in FIG. 8, for example. In this embodiment, a waveform shaping circuit 120 that shapes the waveform of the flyback pulse generated by the transformer 2,
A differentiating circuit 121, a waveform shaping circuit 120 and a differentiating circuit 121 for differentiating a horizontal drive (HD) pulse generated in synchronization with a horizontal synchronizing signal by a horizontal drive pulse generating circuit (not shown).
A charge / discharge control signal generation circuit 122 for generating a charge / discharge control signal for controlling charge / discharge from the output of the charge / discharge control signal, a charge / discharge circuit 123 for controlling charge / discharge by a charge / discharge control signal generated by the charge / discharge control signal generation circuit 122, A comparison circuit 124 that compares the output of the charge / discharge circuit 123 with a reference level, a feedback circuit 125 that peak-rectifies the output voltage of the capacitor 74, synthesizes it with the reference level, and feeds it back to the comparison circuit 124, the comparison circuit 1
An output circuit 126 for outputting the output of 24 to a circuit (not shown),
And a clamp circuit 127 that clamps the output of the charge / discharge circuit 123 supplied to the comparison circuit 126 to a predetermined level.
It is composed by.

The waveform shaping circuit 120 is composed of a resistor 81 and a Zener diode 82. Differentiator circuit 12
1 is composed of resistors 83, 85, 87, 89, 90, capacitors 84, 88, and NPN transistor 86. The charge / discharge control signal generation circuit 122 includes a comparator 91. The charge / discharge circuit 123 includes a resistor 92,
94, 95, PNP transistor 93, capacitor 96
It is composed by. The comparison circuit 124 includes a capacitor 97, resistors 98 and 100, and a comparator 99, and the feedback circuit 125 includes a diode 101, a capacitor 103, and a resistor 102. Output circuit 1
Reference numeral 26 is a resistor 104, 105, an NPN transistor 10
6, PNP transistor 107.
Further, the clamp circuit 127 includes a capacitor 108 and a resistor 1.
09 and the diode 110.

Next, the operation will be described with reference to the timing chart of FIG. When the level of the flyback pulse (FIG. 9A) generated corresponding to the horizontal deflection period exceeds a predetermined value, the Zener diode 82 becomes conductive and its cathode is clamped to a predetermined voltage. Therefore, the cathode voltage of the Zener diode 82 is as shown in FIG.
As shown in (b). In addition, the horizontal drive pulse (see FIG.
(C) is differentiated by a differentiating element composed of a capacitor 84 and a resistor 85, and its phase is inverted by an NPN transistor 86 (FIG. 9 (d)).

The comparator 91 compares the output of the Zener diode 82 (FIG. 9 (b)) with the output of the NPN transistor 86 (FIG. 9 (d)), and the output is a logic H (when the former is larger than the latter. Or open state), and when it is small, it is inverted to logic L (FIG. 9 (e)).

The PNP transistor 93 functions as a constant current circuit because a constant voltage is applied to its base by the resistors 94 and 95. When the comparator 91 outputs a logic H, the constant current charges the capacitor 96. To be done.
When the comparator 91 outputs a logic L, the charge charged in the capacitor 96 is absorbed by the comparator 91 and is instantly discharged. As a result, a voltage (FIG. 9F) that changes into a sawtooth wave in the horizontal deflection period is generated in the capacitor 96.

It should be noted here that this sawtooth wave is generated with reference to the flyback pulse within the same horizontal deflection period. That is, normally, due to the time delay of the signal processing, as shown in FIG. 10, the sawtooth wave of the next horizontal deflection cycle is generated in synchronization with the flyback pulse 1H (horizontal deflection cycle) before. .. The horizontal drive pulse (and therefore the flyback pulse generated in synchronization with it) normally keeps its frequency constant, so
Servo is applied. Therefore, the time axis of the flyback pulse before 1H is different from that of the flyback pulse after 1H. As a result, as shown in FIG.
When the next H sawtooth wave is generated in synchronization with the previous flyback pulse, it is affected by the noise due to this AFC,
The operation tends to be unstable. On the other hand, when the sawtooth wave is generated using the flyback pulse in the same H as a reference as in the above embodiment, the influence of this AFC can be reduced.

The voltage of the capacitor 96 is supplied to the inverting input terminal of the comparator 99 via the DC blocking capacitor 97. A resistor 100 is connected to the non-inverting input terminal of the comparator 99.
A reference signal (FIG. 9g) whose level changes in a parabola shape in the vertical deflection period is supplied via. In FIG. 9, since the time axis is based on the horizontal deflection period, the reference signal in FIG. 9g is represented almost as a straight line.

The comparator 99 outputs a logic L when the level of the sawtooth wave signal at the inverting input terminal is higher than the reference signal level at the non-inverting input terminal, and a logic H when the level is lower (FIG. 9).
(H)). Since the reference level (FIG. 9g) changes in the vertical deflection cycle, this signal becomes a PWM signal in which the pulse width of its logic L changes in the vertical deflection cycle. This PWM signal is sent to the NPN transistor 106 and the PNP transistor 107.
Is output via.

The voltage V ₇₄ generated in the capacitor 74 corresponding to the switching of the switch 73 is the feedback circuit 1
25 is rectified by the diode 101, and the capacitor 1
The peak value is held in 03. This holding voltage is combined with the reference level via the resistor 102 and fed back to the non-inverting input terminal of the comparator 99. Therefore, feedback without phase delay can be applied to the control system, and the operation can be stabilized.

By the way, due to variations in transistors (not shown) in the horizontal output circuit, temperature characteristics, high-voltage load fluctuations, etc., as shown in FIGS.
When the storage time represented by the difference between the timing of the rising edge of the horizontal drive pulse and the timing of the rising edge of the flyback pulse fluctuates, as shown in FIG.
The edge of the inverted differential signal output from the collector of the N-transistor 86 also changes. As a result, the clamp circuit 1
When 27 is not provided, the rising timing of the sawtooth wave voltage output from the capacitor 96 also changes, as shown in FIG. As a result, the pulse width of the PWM signal will change even if the reference level shown in FIG. 11e is constant.

Therefore, in the present embodiment, the clamp circuit 127 is connected between the connection point of the resistors 94 and 95 of the charge / discharge circuit 123 and the inverting input terminal of the comparator 99. The potential at the connection point between the resistors 94 and 95 is a constant potential because it is a potential obtained by dividing a predetermined reference potential.
As a result, the maximum potential of the inverting input terminal of the comparator 99 is clamped to a potential lower than this constant potential by the voltage drop of the diode 110. This allows the condenser 96
As shown in FIG. 11F, the sawtooth wave voltage supplied to the inverting input terminal of the comparator 99 has a position of the line of the inclined portion even if the rising timing is deviated in response to the change in the storage time. Is constant. Therefore, if only the range above this inclined portion is used, it is not necessary to be affected by the storage time.

The horizontal pin distortion can be corrected by driving the FET 41 with the PWM signal thus generated.

However, in the embodiment shown in FIG. 8, since the peak of the sawtooth wave is clamped, there are many variations in the vicinity of the rising edge (the start portion of the inclined portion), and it cannot be used. Further, since the slope of the sawtooth wave is related to the gain of the circuit, it cannot be set too large. This gradient can be increased by increasing the power supply voltage, but there is actually a limit to increasing the power supply voltage. For this reason, in the embodiment of FIG. 8, it is necessary to set the rising timing of the sawtooth wave considerably before the rising timing of the flyback pulse. However, when the rising edge of the sawtooth wave is set to an early timing as described above, the voltage V ₇₄ generated at the terminal of the capacitor 74 corresponding to the switching of the switch 73 becomes larger than necessary. In order to prevent this, for example, the structure shown in FIG. 6 can be used.

In the embodiment of FIG. 6, capacitors 151, 152, 154 and a resistor 153 are added in the waveform shaping circuit 120 to the case of the embodiment of FIG. Further, the output circuit 126 has resistors 156, 159, F
An ET 157 and a capacitor 158 are added. Further, a diode 155 is added to the clamp circuit 127. In the present embodiment, the clamp circuit 12 is also used.
The output of No. 7 is supplied to the comparison circuit 124 (comparator 99) via the trapezoidal sawtooth wave signal generation circuit 128. The trapezoidal sawtooth wave signal generation circuit 128 includes a resistor 16
1, 162, 166, 171, 172, capacitor 16
3, 165, 168, diode 173, zener diode 167, PNP transistor 170, comparator 16
It is composed of four. Other configurations are similar to those in FIG.

Next, the operation will be described with reference to the timing chart of FIG. As described above, the horizontal drive pulse is differentiated by the differentiation circuit 121 and supplied to the charge / discharge control signal generation circuit 122. Further, the flyback pulse shown in FIG. 7A is waveform-shaped by the waveform shaping circuit 120 and supplied to the charge / discharge control signal generation circuit 122. A charge / discharge circuit 123 generates a sawtooth wave corresponding to the charge / discharge control signal generated by the charge / discharge control signal generation circuit 122, and the peak of the sawtooth wave is clamped by the clamp circuit 12.
It is clamped at 7 to obtain a sawtooth wave as shown in FIG.

The sawtooth wave signal output from the clamp circuit 127 is input to the non-inverting input terminal of the comparator 164, and the resistors 161 and 162 and the capacitor 16 are input to the inverting input terminal thereof.
3 is compared with a reference voltage d (FIG. 7d) supplied from a circuit consisting of three. In the comparator 164, the sawtooth wave signal is the reference voltage d.
When it is larger, the logic H is output, and when it is smaller, the logic L is output.

A constant voltage is supplied to the base of the PNP transistor 170 whose emitter is connected to a predetermined voltage source through the resistor 169 from a series circuit including a resistor 171, a diode 173, and a resistor 172. Therefore, the PNP transistor 170 operates as a constant current source.
When the output of the comparator 164 is logic H, the constant current output from the collector of the PNP transistor 170 charges the capacitor 168 with the constant current via the Zener diode 167. Then, when the output of the comparator 164 is logic L, the charge stored in the capacitor 168 is equal to that of the comparator 1.
It is absorbed by 64 and discharges. In this way, a trapezoidal sawtooth wave signal as shown in FIG. 7C appears in the capacitor 168. The voltage of the capacitor 168 is the capacitor 165.
Is supplied to the inverting input terminal of the comparator 99 via a circuit composed of a resistor 166 and a resistor 166.

The height h of the trapezoidal portion of the trapezoidal sawtooth wave signal is set by the Zener diode 167. Further, the timing of the rising edge of the flyback pulse (FIG. 7 (a)) and the rising edge of the trapezoidal sawtooth wave signal (FIG. 7 (c)) are
It can be adjusted by changing the reference voltage d. The higher the reference voltage d is, the closer the two timings are. The lower the reference voltage is, the farther the timings are.

By the way, in the CRT, when the image displayed on the CRT becomes bright, the luminance current increases and the high voltage load also increases. As a result, the actually output high voltage decreases. When the high voltage drops, the image size on the screen expands horizontally. Therefore, in order to prevent this, the voltage is normally supplied to the non-inverting input terminal of the comparator 99.
A voltage that changes in a parabolic shape with the vertical deflection period (Fig. 7 (b)).
Servo is applied so that the DC component of the voltage d in Fig. 9 and the DC component of voltage g in Fig. 9 (f) shifts (becomes smaller) in the negative direction, for example. When this parabola voltage is shifted in the negative direction, the terminal voltage of the capacitor 74 increases, and therefore the voltage fed back from the feedback circuit 125 also increases, zooming correction is performed, and the image size is reduced in the horizontal direction. As a result, a fixed image size is basically maintained.

However, when the DC component of the parabola voltage shifts in this way, the pin distortion correction amount also changes. This will be further described with reference to FIGS. 3 and 4. Now, assuming that the screen changes from a dark screen (cutoff) to a bright screen (highlight), the parabola voltage level is lowered as shown in FIG. 4A. As shown in FIG. 4A, the parabola voltage has a small level at its ends (start point and end point) and a large level at the central part in the vertical deflection cycle, but since it has been DC-shifted now, its end The shift amount ΔV ₁ in the central portion and the shift amount ΔV ₂ in the central portion are equal. However, when the parabola voltage is shifted in a DC manner in this way, as shown in FIG. 4B, the feedback change amount Δv _{2 at} the central portion of the vertical deflection cycle in the feedback circuit 125 is the feedback change amount at the end portion. It becomes smaller than Δv ₁ . That is, the change amount Δv of the feedback voltage fluctuates in the vertical deflection cycle.
This is for the following reason.

That is, the current I ₇₄ flowing from the primary coil 32 of the flyback transformer 2 into the capacitor ₇₄ is
As shown in FIG. 13F, the current flows in correspondence with the off period of the switch 73 (FIG. 13E). FIG. 3 shows this current I ₇₄ in an enlarged manner. As shown in the figure, in the case of a bright screen, the inclination is larger and the rising timing is earlier than in the case of a dark screen. Therefore, as shown in FIG. 4 (a), when the parabolic voltage is lowered in a direct current manner, the region of the current I ₇₄ used for generating the PWM signal moves to the right side in the figure, as shown in FIG. Become. Assuming that the time range used for PWM signal generation (width in the horizontal direction in FIG. 3: width indicated by H / L (highlight) and C / O (cutoff) in FIG. 3) is the same on a bright screen and a dark screen, If the area moves to the right, the current I
_Since the level of ₇₄ becomes smaller, the amount of change in energy (the amount of change in the hatched area in the figure) also becomes smaller.

As is apparent from the comparison between FIG. 3 and FIG. 4, the current I ₇₄ becomes smaller when the parabolic voltage is large (the cutoff is achieved) and is larger when the parabolic voltage is small (the highlight is increased). .. Therefore, the change rate of the current I ₇₄ (energy of PWM) when the parabolic voltage is large is
It is smaller than the rate of change when the parabola voltage is small. Since the level corresponding to the charging voltage to the capacitor ₇₄ by the current I ₇₄ is fed back to the comparator 99, the rate of change Δv ₂ of the feedback amount (at the central portion of the parabolic voltage) when the parabolic voltage is large is It is smaller than the change rate Δv ₁ (at the end of the parabola voltage) when it is small.

As a result, the components shown in FIG.
As shown in FIG. 4C, the pin distortion correction amount (AC component) obtained by adding the feedback amount shown in FIG. 4B is brighter in the central portion of the vertical deflection cycle than in the dark screen. Is smaller.

In order to prevent such a change in the vertical deflection cycle of the pin distortion correction amount, for example, the configuration shown in FIG. 1 can be adopted. In this embodiment, at the base of the PNP transistor 170 in the clamp circuit 128,
A tilt adjusting circuit 129 is connected. Also, the comparator 9
The reference level supplied to 9 is phase-compensated by the phase compensation circuit 130.

The inclination adjusting circuit 129 is composed of a parallel circuit of an AC component adjusting circuit 129a and a DC component adjusting circuit 129b, and outputs a signal (ABL signal in the case of example) corresponding to a load fluctuation supplied from a circuit not shown. The PNP transistor 170 is processed to have a predetermined characteristic and output to the base of the PNP transistor 170. The AC component adjusting circuit 129a includes a parallel circuit of a diode 182 and a resistor 181, and a capacitor 183 and a resistor 184 connected in series with the parallel circuit. In addition, the DC component adjusting circuit 129b
Is an integrating circuit composed of a resistor 185 and a capacitor 186, and a resistor 187 and a capacitor 1 connected in series to the integrating circuit.
88 parallel circuits. Further, the phase compensation circuit 130 is composed of an integrating circuit including a resistor 191 and a capacitor 192. Other configurations are shown in FIG.
It is similar to the case in.

The diode 182 compensates for the delay of the AC component of the ABL signal. The DC component of the ABL signal is blocked by the capacitor 183 from passing through the AC component adjusting circuit 129a. Further, the ABL signal is integrated by the resistor 185 and the capacitor 186, and its DC component is detected.
The AC component and the DC component of the ABL signal are combined and supplied to the base of the PNP transistor 170 of the clamp circuit 128. As a result, when the screen is bright (highlight), the base voltage of the PNP transistor 170 is lowered, and the inclination of the trapezoidal sawtooth wave signal is adjusted to be large. On the contrary, when the screen is dark (cutoff), the base voltage of the PNP transistor 170 rises, and the inclination of the trapezoidal sawtooth wave signal is adjusted to be small.

FIG. 5 shows how the slope of the trapezoidal sawtooth wave signal increases at highlight and decreases at cutoff. In this way, when the inclination of the trapezoidal sawtooth wave signal is adjusted, the rate of change Δv in the feedback amount can be made constant during highlighting and during cutoff. Therefore, it is possible to prevent the correction amount of the pin distortion from changing due to the zooming correction.

The parabola voltage is integrated by an integrator circuit including a resistor 191 and a capacitor 192, and then supplied to the non-inverting input terminal of the comparator 99 via the resistor 100. The feedback circuit 125 is a diode 101 and a capacitor 1.
A direct current component to be fed back is detected by the integrating circuit of 03. As a result, the phase compensation circuit 1
In the absence of 30, the feedback component indicated by the solid line is delayed in phase with respect to the voltage symmetrical with the parabola voltage indicated by the dotted line, as shown in FIG. Therefore, the pin distortion correction amount obtained by adding the parabola voltage and the feedback voltage is locally deviated from the original characteristic indicated by the broken line in the figure. This causes a so-called sexy distortion in which the vertical lines have fluctuations.

However, in the present embodiment, the parabola voltage is integrated by the phase compensation circuit 130 so as to correspond to the integrated amount in the feedback circuit 125. As a result, as shown in FIG. 2B, a phase lag also occurs in the parabola voltage corresponding to the feedback component, and fluctuations do not occur in the pin distortion correction amount obtained by adding both, and therefore, , The occurrence of sexy distortion is prevented.

[0075]

As described above, according to the switch drive circuit of the present invention, since the reference level is phase-compensated, the sexy distortion can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a switch drive circuit of the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment of FIG.

3 is a diagram illustrating a relationship between a current flowing through a capacitor 74 in FIG. 12 and a trapezoidal sawtooth wave generated by a trapezoidal sawtooth wave generation circuit 128 in FIG.

FIG. 4 is a diagram illustrating a relationship between a parabola wave and a pin distortion correction amount.

FIG. 5 is a diagram for explaining the operation of the embodiment of FIG.

FIG. 6 is a circuit diagram showing a configuration of a circuit which is a basis of the embodiment of FIG.

FIG. 7 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 8 is a circuit diagram showing a configuration of an embodiment of a circuit which is a basis of the embodiment of FIG.

9 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 10 is a diagram illustrating how a sawtooth wave is generated with reference to a flyback pulse 1H before.

FIG. 11 is a timing chart explaining the operation of the clamp circuit 127 in the embodiment of FIG.

FIG. 12 is a circuit diagram showing a configuration of an embodiment of a deflection current generating circuit to which the switch driving circuit of the present invention is applied.

13 is a timing chart illustrating the operation of the embodiment of FIG.

FIG. 14 is a circuit diagram showing a configuration of a second embodiment of a deflection current generating circuit to which the switch driving circuit of the present invention is applied.

15 is a timing chart illustrating the operation of the embodiment of FIG.

16 is a circuit diagram showing a configuration example of a transformer applicable in the embodiments of FIGS. 12 and 14. FIG.

FIG. 17 is a circuit diagram showing a configuration of a third embodiment of a deflection current generating circuit to which the switch driving circuit of the present invention is applied.

FIG. 18 is a timing chart for explaining the operation when the DC component of the current I ₃₂ changes in the embodiments of FIGS. 12, 14 and 17.

FIG. 19 is a circuit diagram showing a configuration of a fourth embodiment of a deflection current generating circuit to which the switch driving circuit of the present invention is applied.

20 is a diagram for explaining the operation of the coil 63 in the embodiment of FIG.

FIG. 21 is a block diagram showing a configuration example of a conventional horizontal deflection circuit.

22 is a circuit diagram showing a configuration example of the horizontal deflection circuit 1 in the example of FIG.

FIG. 23 is a timing chart illustrating the operation of FIG. 22.

FIG. 24 is a diagram illustrating the principle of horizontal pin generation in the example of FIG. 22.

FIG. 25 is a circuit diagram showing a configuration of an example of a conventional deflection current generating circuit that corrects a horizontal pin.

FIG. 26 is a waveform diagram illustrating the operation of the example of FIG.

[Explanation of symbols]

 1 Horizontal Deflection Circuit 2 Transformer 6 CRT 7 Deflection Yoke 22 NPN Transistor 23 Diode 24, 25 Capacitor 31 Power Supply 32 Coil 33, 34 Switch 35 Capacitor 36 Coil 37 Capacitor 38 Coil 39 Power Supply 41 FET 71, 72 Control Circuit 73 Switch 74 Capacitor 61 Secondary coil 62 Capacitor 63 Coil 120 Waveform shaping circuit 121 Differentiating circuit 122 Charging / discharging control signal generating circuit 123 Charging / discharging circuit 124 Comparison circuit 125 Feedback circuit 126 Output circuit 127 Clamp circuit 128 Trapezoidal sawtooth wave signal generating circuit 129 Inclination adjusting circuit 130 Phase compensation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiji Kawabe 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (1)

[Claims] 1. A switch drive circuit for driving a switching element that switches in accordance with a horizontal deflection cycle and a vertical deflection cycle, wherein a waveform shaping circuit for shaping a flyback pulse corresponding to the horizontal deflection cycle and a horizontal deflection cycle A differentiating circuit that differentiates the corresponding horizontal drive pulse, a charge / discharge control signal generating circuit that generates a charge / discharge control signal from the outputs of the waveform shaping circuit and the differentiating circuit, and a charge / discharge charging / discharging control signal corresponding to the charge / discharge control signal. A discharge circuit, a clamp circuit that clamps the output of the charge / discharge circuit to a predetermined level, a trapezoidal sawtooth wave signal generation circuit that generates a trapezoidal sawtooth wave signal from the output of the clamp circuit, and the trapezoidal sawtooth wave signal A comparison circuit for comparing the trapezoidal sawtooth wave signal generated by the generation circuit with a reference level corresponding to the vertical deflection period, Switch driving circuit comprising: a phase compensation circuit for phase compensating the reference level.