JPH0583578A - Deflected current generating circuit - Google Patents

Abstract

PURPOSE:To correct intermediate pin distortion. CONSTITUTION:A first resonance circuit is composed of a horizontal deflecting coil 7 and capacitors 25, 81 and 24, and a second resonance circuit is composed of a second-order coil 61 of a transformer 2, coil 63 and capacitors 81, 74. Both resonance currents flow to the capacitor 81. The first and second resonance circuits are respectively switched by an NPN transistor 22 and an FET 73. The switching of the transistor 22 is controlled only in the horizontal deflecting cycle, and the switching of the FET 73 is controlled corresponding to not only the horizontal deflecting cycle but also the vertical deflecting cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deflection current generating circuit suitable for use in, for example, television receivers, monitor devices and the like.

[0002]

2. Description of the Related Art FIG. 14 shows a conventional configuration example of a horizontal deflection circuit and a circuit in the vicinity thereof in a television receiver. A power supply 3 is connected to the horizontal deflection circuit 1 via a primary coil 2 a of a flyback transformer 2. A rectifying / smoothing circuit including a diode 4 and a capacitor 5 is connected to the secondary winding 2b of the transformer 2. The horizontal deflection current output from the horizontal deflection circuit 1 is the CR having the screen 6a.
It is adapted to be supplied to the deflection yoke 7 of T6.

FIG. 15 shows the internal construction of the horizontal deflection circuit 1. In this example, the horizontal deflection circuit 1 has N
A parallel circuit including a PN transistor 22, a diode 23, and a capacitor 24 is connected in parallel with a series circuit of the deflection yoke 7 and the capacitor 25. Also, in this example, the transformer 2 and the secondary coil 2 are
c is provided, and its output is rectified by the diode 21 and output.

Next, the operation will be described. Power supply 3
The DC voltage output from the primary coil 2a of the transformer 2
Is supplied to the collector of the NPN transistor 22 via. The NPN transistor 22 is turned on / off by supplying a signal corresponding to the horizontal deflection period to its base. As a result, a flyback pulse (retrace pulse) Vcp as shown in FIG. 16B is generated at the collector of the NPN transistor 22.

Capacitors 24 and 25 and deflection yoke 7
Constitutes a resonance circuit, and performs resonance operation corresponding to the switching operation of the NPN transistor 22. As a result, as shown in FIG. 16A, a so-called sawtooth wave deflection current I ₇ that linearly increases in the trace section and linearly decreases in the retrace section flows in the deflection yoke ₇ . As a result, the electron beam is scanned (deflected) in the horizontal direction on the screen 6a of the CRT 6.

The flyback pulse voltage Vcp is
The voltage is boosted by the secondary coil 2c of the flyback transformer 2 and rectified by the diode 21 to generate the high voltage Hv. This high voltage Hv is supplied to the anode of the CRT 6. Further, the voltage output from the secondary coil 2b is rectified by the diode 4 and smoothed by the capacitor 5 to become the DC voltage Vc. This voltage Vc is used as a focus voltage of the CRT 6, a heater voltage, and the like.

By the way, as shown in FIG. 17B, the distance from the electron gun 6b to the screen 6a is shortest at the center of the screen 6a and longest at the upper end or the lower end of the screen 6a. As a result, so-called horizontal pins (PIN) are generated as shown in FIG. If this horizontal pin is left as it is, the displayed image will be distorted. Therefore, a circuit for correcting the horizontal pin is usually added to the horizontal deflection circuit.

FIG. 18 shows the principle of the horizontal deflection circuit disclosed in Japanese Patent Publication No. 57-39102. That is, in this example, the DC voltage output from the power supply 31 passes through the coil 32, the switch 33, and the capacitor 2
4 and the horizontal deflection coil 7 and the capacitor 25 are supplied to a parallel circuit composed of a series circuit. The power supply 31 and the coil 32 correspond to the power supply 3 and the primary winding 2a of the flyback transformer 2 in FIG. The switch 33 corresponds to a parallel circuit including the NPN transistor 22 and the diode 23.

In this example, a switch 34, a capacitor 24, a capacitor 35, and a coil 36 and a capacitor 37 are provided in a parallel circuit (first parallel circuit) including a series circuit of the switch 33, the capacitor 24, the horizontal deflection coil 7 and the capacitor 25. Parallel circuit of a series circuit (second parallel circuit)
Are connected. Then, a series circuit including a coil 38 and a power source 39 is connected in parallel to the second parallel circuit.

That is, the horizontal deflection circuit has a structure in which the first parallel circuit is connected to the second parallel circuit having the same structure as the first parallel circuit.

To correct the horizontal pin, as shown in FIG. 19 (a), a retrace pulse (terminal voltage V _{24 of the} capacitor ₂₄ ) applied to the horizontal deflection coil 7 in accordance with the vertical deflection cycle is It is necessary to adjust so that the level at the substantially central portion (even on the screen) is higher than the levels at the left and right end portions (upper and lower end portions on the screen). The level of the retrace pulse obtained by adding this voltage V ₂₄ and the terminal voltage V ₃₅ of the capacitor 35 is the power supply 31.
Since it is defined by the width of the retrace pulse, it becomes constant as shown in FIG. Therefore, the voltage V
_As shown in FIG. 19B, the value of ₃₅ becomes smaller at the central portion (central portion on the screen) corresponding to the vertical deflection period, and at the left and right end portions (upper and lower end portions on the screen). The terminal voltage V ₂₄ is changed by increasing the voltage
It is possible to adjust the level at the substantially central portion (the central portion on the screen) to be higher than the levels at the left and right end portions (upper and lower end portions on the screen).

Therefore, in this example, the switch 34 is switched at the same timing as the switch 33 to generate a retrace pulse at the connection point between the capacitor 35 and the coil 38, and the voltage output from the power supply 39 is shown in FIG. As shown in (b), the value is changed such that the value becomes smaller at the central portion (central portion on the screen) and increases at the left and right end portions (upper and lower end portions on the screen) corresponding to the vertical deflection cycle. As a result, the voltage V ₂₄ becomes
As shown in FIG. 19A, the level at the substantially central portion (the central portion also on the screen) changes so as to become higher than the levels at the left and right end portions (upper and lower end portions on the screen), The horizontal pin will be corrected.

In addition to this, as a method for correcting the horizontal pin,
The power supply modulation method and the PCT method are known. In the power supply modulation method, for example, in FIG. 15, the voltage of the power supply 3 is modulated in the vertical deflection cycle. In addition, the PCT method is shown in FIG.
5, a secondary winding of a transformer is connected in series to the horizontal deflection coil 7, and a vertical deflection current is passed through the primary winding.

However, in any of these methods,
Since the voltage Vcp is modulated in the vertical deflection cycle, various voltages taken out from the transformer 2 are also modulated in the vertical deflection cycle, and in a so-called separate type circuit in which a horizontal deflection circuit and a high voltage generation circuit are separately provided. Although it can be applied, it has a problem that it cannot be used in a so-called conventional type circuit in which both are integrated. In that respect, the method shown in FIG.
Even when 2 is configured as the primary winding of the transformer, various voltages taken out from the secondary winding are not modulated in the vertical deflection cycle, and are applicable not only to the separate type but also to the conventional type horizontal deflection circuit. Can be used.

[0015]

However, in the circuit having the configuration shown in FIG. 18, since the S-curve correction amount required for the horizontal deflection current changes in vertical synchronization, as shown in FIG.
There is a problem in that the occurrence of so-called intermediate pin distortion cannot be suppressed.

The present invention has been made in view of such a situation, and is intended to further reduce the intermediate pin distortion.

[0017]

In the deflection current generating circuit of the present invention, an NPN transistor 22 as a first switching element which performs a switching operation corresponding to a horizontal deflection period is provided.
And the transformer 2 whose primary winding 32 is connected to the NPN transistor 22 so as to generate the retrace pulse in response to the switching operation of the NPN transistor 22, and the resonance corresponding to the switching operation of the NPN transistor 22. The horizontal deflection coil 7, the capacitors 24 and 25 as the operating first resonance circuit, and the second switching operation corresponding to both the horizontal deflection period and the vertical deflection period.
73 as a switching element of the
The coil 6 as the second resonance circuit connected to the secondary coil 61 of the transformer 2 and the capacitor 25 of the first resonance circuit so as to perform resonance operation corresponding to the switching operation of
3, and the first resonance circuit and the second resonance circuit each have a capacitor 81 as a common capacitor at a position where each resonance current flows.

[0018]

In the deflection current generating circuit having the above structure, the FE
T73 is switched according to the horizontal deflection cycle, and the switching operation itself is controlled according to the vertical deflection cycle. Further, a capacitor 81 is arranged commonly to the first resonance circuit and the second resonance circuit. When the charging voltage of the capacitor 81 decreases, the S-shaped correction amount decreases. Therefore, it becomes possible to correct the intermediate pin distortion.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a circuit diagram showing a configuration of an embodiment which is a premise of a deflection current generating circuit of the present invention.
18 and the parts corresponding to those in FIG. 18 are designated by the same reference numerals. In this embodiment, switch 3
3, condenser 24, horizontal deflection coil 7 and condenser 2
A parallel circuit composed of a series circuit of 5 is connected in series with a parallel circuit of a switch 73 and a capacitor 74. The switch 33 is controlled by the control circuit 71 in accordance with the horizontal deflection cycle, and the switch 73 is controlled by the control circuit 72 in accordance with the horizontal deflection cycle and the vertical deflection cycle. ing.

Next, the operation will be described with reference to the timing chart of FIG. The switch 33 is controlled by the control circuit 71 to be turned on during the horizontal deflection trace section and turned off during the retrace section (FIG. 3B). Coil 32
The sawtooth current I ₃₂ (FIG. 3A) flowing through the switch flows through the switch 33 when the switch 33 is on and through the capacitor 24 when the switch 33 is off. The switch 73 is controlled by the control circuit 72, and is turned off for a predetermined time in the retrace period in which the switch 33 is off (FIG. 3 (e)). The current I ₃₂ is the switches 33 and 73.
When is on, these switches 33 and 73 flow,
When both switches 33 and 73 are off, they flow through capacitors 24 and 74. When the switch 33 is off and the switch 73 is on, the capacitor 24 and the switch 73 flow. When the switch 33 is off, the sawtooth current I ₇ flows through the resonance circuit including the horizontal deflection coil 7 and the capacitors 25 and 24.

The capacity of the capacitor 24 is the same as that of the capacitor 74.
It is set to a value smaller than the capacity of. Therefore, the length (time) Tr of the retrace period is substantially equal to that of the capacitor 24.
And 25, and the inductance of the horizontal deflection coil 7, even if the capacitor 74 is connected,
It takes almost the same time as when not connecting. Coil 3
It is known that the voltage Vcp between the connection point of 2 and the horizontal deflection coil 7 and the ground potential is obtained by the following equation. Vcp = E (1+ (π / 2) (Tt / Tr)) (1)

This voltage Vcp is equal to the sum of the terminal voltage V ₂₄ of the capacitor ₂₄ and the terminal voltage V ₇₄ of the capacitor 74. That is, the following equation is established. Vcp = V ₂₄ + V ₇₄ (2)

The energy for deflection is stored in the condenser 7
4 is not connected, (1/2) C ₂₄ Vcp ² is obtained, but when the capacitor 74 is connected as shown in FIG. 2, it becomes (1/2) C ₂₄ V ₂₄ ² . Since V ₂₄ is smaller than Vcp, capacitor 74
The deflection current I ₇ is reduced in the case where the connection is made as compared with the case where the connection is not made. Therefore, when the voltage V ₇₄ is adjusted by adjusting the period during which the switch 73 is off (the period during which the switch 73 is on), the voltage V ₂₄ can be consequently adjusted, and further the deflection current I ₇ can be adjusted. As a result, it becomes possible to adjust the raster size. Further, the left and right pins can be corrected by adjusting the period during which the switch 73 is turned off in the vertical deflection cycle.

This will be further described with reference to FIG. 3. In the lithographic section in which the switch 33 is off, the capacitor 24 has a combined current I ₃₂ of the current I ₃₂ and the current I _7.
24 (Fig. 3 (c)) flows. Current I ₃₂ and I ₇ current I _{2 4} for both a current of sawtooth becomes as shown in Figure 3 (c). For example, when the switch 73 is turned on and off at exactly the same timing as the switch 33, the current I ₃₂ flows to the ground via the switch 73 or the capacitor 74, so the current I ₇₄ is the switch 33 (or 73).
Is equal to the current flowing through the capacitor 24 in the off period.

As shown in FIG. 3E, when the switch 73 is turned off later than the switch 33 is turned off (FIG. 3B), the switch 3 is turned off.
When the switch 3 is off and the switch 73 is on, the current I
_{Although 32} flows through the switch 73, it flows through the capacitors 24 and 74 when both the switches 33 and 73 are off. Therefore, the current I ₇₄ has a waveform shown by the solid line in FIG. 3F (a waveform obtained by cutting out the current I ₃₂ ). That is, by adjusting the timing of turning off the switch 73, it is possible to change and adjust the section in which the current I ₃₂ is cut out, and the current I ₇₄ is similar to the current I _{32 in} that the width and height change at the same ratio. Form a current waveform. Therefore, the voltages V ₂₄ and V ₇₄ (FIGS. 3D and 3G) generated in the capacitors 24 and 74 have substantially similar voltage waveforms although the resonance frequencies are different. As a result, if the OFF timing of the switch 73 is adjusted in accordance with the vertical deflection period, the current I ₇₄ flowing through the capacitor 74, and hence the voltage V ₇₄ generated there, changes, and as a result, the capacitor 24 changes. The generated voltage V ₂₄ changes (FIGS. 3D to 3G).

In this case, since the coil 38 and the power source 39 shown in FIG. 18 are omitted, it is not necessary to supply energy from the coil 32 to the coil 38 and the energy consumed is reduced accordingly. be able to.

FIG. 4 shows the configuration of the second embodiment which is the premise of the deflection current generating circuit of the present invention. In this embodiment, the switch 33 in the embodiment of FIG.
The parallel circuit of the transistor 22 and the diode 23 is formed, and the switch 73 is formed of the parallel circuit of the FET 41 and the diode 42. Other configurations are shown in FIG.
It is similar to the case in.

FIG. 5 is a timing chart showing the operation of the embodiment shown in FIG. As shown in FIG. 5A, the NPN
When the FET 41 is turned off as shown in FIG. 7C while the transistor 22 is off, the terminal voltage V ₇₄ of the capacitor 74 becomes as shown in FIG.
The retrace pulse voltage Vcp at the connection point between the coil 32 and the horizontal deflection yoke 7 is, as shown in FIG. 5B, the terminal voltage V _{74 of the} capacitor 74 shown in FIG. 5D and the capacitor shown in FIG. It is the sum of ₂₄ terminal voltages V ₂₄ . Therefore, the frequency (width) and height of the pulse voltage V ₇₄ generated at both ends of the capacitor 74 can be adjusted by adjusting the timing when the FET 41 is turned off in accordance with the vertical deflection period. Here, increasing the frequency means reducing the width of the pulse shown in FIG. 5D, and decreasing the frequency means increasing the width of this pulse. When the width of the pulse is narrow, the height of the pulse is low, and when the width is wide, the height of the pulse is high. As a result, the voltage Vc
The voltage V _{24 obtained} by subtracting the voltage V ₇₄ from p (constant) is shown in FIG.
It will change as shown in.

Although only the OFF period of the NPN transistor 22 and the FET 41 is shown in FIG. 5, the ON timing of the diodes 23 and 42 is when the voltage Vcp becomes 0 or the voltage V _{74, respectively.} It is a match when becomes 0. Therefore, when the NPN transistor 22 and the diode 23 are regarded as one switch 33, and the FET 41 and the diode 42 are regarded as one switch 73, the operation is the same as in the case of FIG.

The coil 32 shown in FIGS. 2 and 4 can be constructed as a primary coil of the flyback transformer 2 as shown in FIG. In this case, 51 and 54 are provided as secondary coils. The output of the secondary coil 51 is rectified by the diode 52, divided by the resistor 53, and output as the focus voltage. The outputs of the secondary coil 54 are output as pulses having mutually opposite polarities.

FIG. 7 shows a third embodiment of the presupposed circuit. In this embodiment, the emitter of the NPN transistor 22 in the embodiment shown in FIG. 4 is grounded. Other configurations are similar to those in FIG. Even in the case of such a configuration, the same operation as in the case shown in FIG. 4 can be executed.

By the way, in the embodiment shown in FIGS. 2, 4 and 7, if the DC component of the current I ₃₂ flowing through the coil 32 fluctuates as shown in FIG. In response to the switching operation of the switch 73 shown in (), a current I ₇₄ flows through the capacitor 74 as shown in FIG. That is, at this time, in the state in which the DC component is superimposed (the state shown on the right side in FIG. 8), the current I ₇₄ changes non-linearly, and the terminal voltage V ₇₄ of the capacitor ₇₄ is
It varies as shown in (d). This means that the coil 32
A change in the current I ₃₂ flowing through the line means that the raster size changes. Therefore, although it can be applied to a so-called separate type circuit in which the horizontal deflection circuit and the high voltage generating circuit are separately provided, it is not suitable for a so-called conventional type circuit in which the both are integrated.

From this point of view, FIG. 9 is designed so that it can be used also in a conventional type circuit. In this embodiment, the transformer 2 is composed of a primary coil including a coil 32 and a secondary coil 61. The secondary coil 61 is connected to the connection point between the capacitor 74 and the capacitor 25 via the series circuit of the coil 63 and the capacitor 62. Other configurations are the same as those in the embodiment shown in FIGS. 2 and 4. That is, in this embodiment, the main resonance circuit including the horizontal deflection coil 7 and the capacitors 25 and 24 is connected to the sub-resonance circuit including the secondary coil 61, the coil 63, the capacitor 62, and the capacitor 74. Is becoming

With this structure, current flows through the path of the capacitor 74, the capacitor 62, the coil 63, and the secondary coil 61 of the transformer 2 in the first half of the retrace section, and the reverse path in the latter half of the retrace section. A current I ₆₃ flows through the coil 63.

The frequency of the trace interval in the main resonant circuit is defined by the capacitance C ₂₅ of the inductance L ₇ and capacitor 25 of the horizontal deflection coil 7, in retrace interval L ₇ and C _25, and the electrostatic capacitor 24 It is defined by the capacitance C ₂₄ . Further, in the sub-resonance circuit, the capacitance of the capacitor 62 is C in the trace section.
₆₂ and the inductance M _{63 of the} coil 63 (described later), and in the retrace section, M ₆₃ and C ₆₂ and the capacitance C ₇₄ of the capacitor 74 (Table 1
reference).

[Table 1]

In the main resonance circuit and the sub-resonance circuit, the frequency f _T in the trace section needs to be set to a value sufficiently smaller than the frequency f _{R in the} retrace section. That is, the trace section needs to be set to a time sufficiently longer than the retrace section. To achieve this, C ₆₂
Is set to a value sufficiently larger than C ₇₄ .

That is, the frequencies f _T and f _R are expressed by the following equations. f _T = 1 / (2π (M ₆₃ C ₆₂ ) ^1/2 ) ・ ・ ・ ・ ・ (3) f _R = 1 / (2π (M ₆₃ C ₀ ) ^1/2 ) ・ ・ ・ ・ ・ (4) Here, C ₀ is a series combined capacitance of the capacitors 62 and 74, and is represented by the following equation. C ₀ = C ₆₂ C ₇₄ / (C ₆₂ + C ₇₄ ) ... (5) Further, M ₆₃ is not the original inductance L ₆₃ of the coil ₆₃ , but is defined according to the voltage applied across the coil 63. Is the inductance.

That is, as shown in FIG. 10, the terminal voltage V ₇₄ of the capacitor ₇₄ and the output voltage V ₆₁ of the secondary coil 61 of the transformer 2 are applied to one terminal and the other terminal of the coil 63. As a result, the inductance M ₆₃ that contributes to the resonant operation of the sub-resonant circuit is expressed by the following equation. M ₆₃ = L ₆₃ V ₇₄ / (V ₇₄ + V ₆₁ ) ... (6)

The virtual ground point of the coil 63 is the voltage V _{74 at} both ends.
And V ₆₁ corresponding to the voltage value of V ₆₁ .

By the way, since f _T is sufficiently smaller than f _R ,
The following equation holds. 1 / (2π (M ₆₃ C ₆₂ ) ^1/2 ) << 1 / (2π (M ₆₃ C ₀ ) ^1/2 ) ... (7) From the above equation, the following equation is obtained. M ₆₃ C ₆₂ >> M ₆₃ C ₀ (8) Rearranging the above equation gives the following. C ₆₂ >> C ₀ (9) Here, if C ₆₂ >> C ₇₄ , the value of C ₀ is almost C _74.
The above equation is satisfied, as defined by.

Further, since the frequency is determined in accordance with the product of M ₆₃ (L ₆₃ ) and C ₇₄ , M ₆₃ (L ₆₃ ) needs to be set to a value sufficiently large for C ₇₄ . ..

Since the coil 61 applies a predetermined bias to the capacitor 74 via the coil 63 and the capacitor 62, the transformer 2 is greatly affected by the current flowing from the coil 63 to the secondary coil 61 of the transformer 2. It is necessary to prevent such things from being received. So 2
The inductance L ₆₁ of the next coil 61 needs to be set to a value sufficiently larger than the inductance L _{63 of the} coil 63.

As described above, the secondary coil 6 of the transformer 2
When the current I ₆₃ is supplied as a bias from 1 to the capacitor 74 through the coil 63 and the capacitor 62, a combined current of I ₃₂ and I ₆₃ flows in the capacitor 74 in a steady state. Therefore, if the current I ₆₃ is set to a value that is sufficiently larger than the current I ₃₂ , even if the current I ₃₂ changes in response to the change in the high voltage applied on the secondary side of the transformer 2, the current I ₃₂ flows to the capacitor 74. The amount of change in current can be relatively small. Therefore, a flyback transformer can be used as the transformer 2, and it can be applied to a so-called conventional type circuit.

The capacitor 62 in FIG. 9 may be connected between the capacitor 25 and the capacitor 74 so as to be shared by the main resonance circuit and the sub resonance circuit. In addition, the emitter of the NPN transistor 22 is shown in FIG.
It can also be grounded, as in.

In the above embodiment, the switch 33 is composed of the NPN transistor 22 and the diode 23 and the switch 73 is composed of the FET 41 and the diode 42. However, the switch 33 is composed of the FET and the diode. The switch 73 can also be composed of a transistor and a diode. Further, both the switches 33 and 73 can be configured by transistors and diodes, or can be configured by FETs and diodes. Further, when the FET is used, its parasitic diode can be used to omit the external diode. Generally, using an FET can simplify the drive and increase the switching speed, as compared with the case where a transistor is used.

By the way, in the above embodiments, the intermediate pin distortion cannot be corrected. In order to correct this intermediate pin distortion, for example, the structure shown in FIG. 1 can be used. In this embodiment, a capacitor 81 is connected as a common element (element through which each resonance current flows) to the main resonance circuit (first resonance circuit) and the sub resonance circuit (second resonance circuit). In this way, when the charging voltage of the capacitor 81 becomes smaller, the S-shaped correction amount becomes smaller, and the S-shaped correction amount necessary for the horizontal deflection current can be adjusted in the vertical cycle. Therefore, it becomes possible to correct the intermediate pin.

Furthermore, as shown in FIG. 11, a capacitor 62 can be connected between the connection point between the capacitors 81 and 25 and the coil 63, as in the embodiment of FIG. By doing so, the S-shaped correction is also added to the resonance current of the sub-resonance circuit, and the correction amount of the intermediate pin distortion can be increased.

The three capacitors 25 and 6 shown in FIG.
The Y-shaped connection of 2, 81 is equivalent to the Δ-shaped connection of the three capacitors 91, 92, 93 as shown in FIG. Here, the capacitances of the capacitors ₂₅ , ₆₂ and ₈₁ are C ₂₅ , C ₆₂ and C ₈₁ , respectively, and the capacitors 91 and 9 are
Each capacitance of 2,93, if the _{C 91, C 92, C 93} , C 91, C 92, C 93 is defined by the following equation. C ₉₁ = C ₂₅ · C ₆₂ / (C ₂₅ + C ₆₂ + C ₈₁ ) C ₉₂ = C ₈₁ · C ₆₂ / (C ₂₅ + C ₆₂ + C ₈₁ ) C ₉₃ = C ₂₅ · C ₈₁ / (C ₂₅ + C ₆₂ + C ₈₁ Therefore, the embodiment of FIG. 11 can be rewritten as shown in FIG. With the configuration shown in FIG. 13, the capacitance of the capacitor can be reduced, so that the mounting area can be reduced and the device can be downsized.

In the embodiment of FIG. 11, the capacitor 25 can be omitted if necessary. In this case, the capacitor 81 plays a role as a power source in the main resonance circuit. In this way, FIG.
It is possible to reduce the number of elements while having substantially the same intermediate pin correction amount as in the above embodiment.

[0050]

As described above, according to the deflection current generating circuit of the present invention, not only the second switching element is switched according to the horizontal deflection cycle, but also controlled according to the vertical deflection cycle. Moreover, since the common capacitor is connected to the first resonance circuit and the second resonance circuit, it is possible to correct the intermediate pin distortion without increasing the power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a deflection current generating circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an embodiment of a circuit which is a basis of the embodiment of FIG.

FIG. 3 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of a circuit which is a basis of the embodiment of FIG.

5 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 6 is a circuit diagram showing a configuration of a transformer applicable in the embodiments of FIGS. 2 and 4.

FIG. 7 is a circuit diagram showing a configuration of a third embodiment of a circuit which is a basis of the embodiment of FIG.

FIG. 8 shows the current I in the embodiment of FIGS. 2, 4 and 7.
₇ is a timing chart illustrating an operation when ₃₂ DC components are changed.

9 is a circuit diagram showing a configuration of a fourth embodiment of a circuit which is a basis of the embodiment of FIG.

FIG. 10 is a diagram for explaining the operation of the coil 63 in the embodiment of FIG.

FIG. 11 is a circuit diagram showing a configuration of a second embodiment of a deflection current generating circuit of the present invention.

FIG. 12 is a diagram illustrating a configuration of an equivalent circuit of a Y connection circuit of a capacitor.

13 is a circuit diagram showing a configuration of an equivalent circuit of the embodiment of FIG.

FIG. 14 is a block diagram showing a configuration example of a conventional horizontal deflection circuit.

15 is a circuit diagram showing a configuration example of a horizontal deflection circuit 1 in the example of FIG.

16 is a timing chart for explaining the operation of FIG.

17 is a diagram illustrating the principle of horizontal pin generation in the example of FIG.

FIG. 18 is a circuit diagram showing a configuration of an example of a conventional deflection current generating circuit that corrects a horizontal pin.

FIG. 19 is a waveform diagram illustrating the operation of the example of FIG.

FIG. 20 is a diagram illustrating intermediate pin distortion.

[Explanation of symbols]

 1 Horizontal Deflection Circuit 2 Transformer 6 CRT 7 Deflection Yoke 22 NPN Transistor 23 Diode 24, 25 Capacitor 31 Power Supply 32 Coil 33, 34 Switch 35 Capacitor 36 Coil 37 Capacitor 38 Coil 39 Power Supply 41 FET 71, 72 Control Circuit 73 Switch 74 Capacitor 61 Secondary coil 62 Capacitor 63 Coil 81 Capacitor

Claims (1)

[Claims] 1. A first switching element that performs a switching operation in response to a horizontal deflection cycle, and a primary winding of the first winding element that generates a retrace pulse in response to the switching operation of the first switching element. A transformer connected to the first switching element, a first resonance circuit that resonates in response to the switching operation of the first switching element, and a switching circuit that responds to both horizontal and vertical deflection cycles. A second switching element that operates and a second resonance that is connected to the secondary coil of the transformer and the first resonance circuit so as to perform resonance operation corresponding to the switching operation of the second switching element. Circuit, and the first resonance circuit and the second resonance circuit have a common capacitor at a position where each resonance current flows. Deflection current generating circuit according to claim.