MXPA99001172A - Frequency lock indicator for fpll demodulated signal having a pilot - Google Patents

Abstract

A biphase stable FPLL includes a polarity determination circuit (36) that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock indicator circuit (50-60) determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming signal (or alternatively, of the outgoing signal) as determined in order to supply an output signal of predetermined polarity. The frequency lock indicator consist of a zero crossings detector (50) and a latch (56) that is sampled for a time period. The zero crossings detector (50) is a delay (52) and an exclusive OR gate (54). An optional confidence counter (60) may be used with the latch (56) to determine when frequency lock has occurred to provide the lock indicator signal.

Description

FREQUENCY SYNCHRONIZATION INDICATOR FOR SIGNAL DEMODULATED BY A FREQUENCY AND PHASE CIRCUIT SYNCHRONIZED THAT HAS A PILOT DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION AND PREVIOUS TECHNIQUE This invention relates in a general manner to demodulation systems and particularly to a demodulation system that incorporates an FPLL (frequency and synchronized phase circuit) to demodulate a residual sideband digital signal (VSB). with a pilot. The FPLL demodulation circuits have been in common use for a number of years and are fully described in U.S. Patent Nos. 4,072,909 and 4,091,410, both of which were granted to the beneficiary of this application and both of which are incorporated herein. as reference. The FPLLs are stable biphasic and as such generally require some mechanism to ensure the proper polarity of the demodulated output signal when, for example, they are used in television receiver circuits and the like. In the circuits of the prior art, an information signal (eg, a data signal) was developed in the output, which includes REF. 29338 a - known component indicating the phase of synchronization or polarity of the FPLL. This component was used to control an inverter to selectively invert the output signal of the FPLL to ensure a particular polarity. The transmitted digital signal used with the invention includes a small pilot in phase to allow acquisition of the signal in the receiver. The pilot is inserted into the data signal before modulation, in the form of a baseband CD counter-tension, and when demodulated in a receiver, produces a corresponding DC voltage. The invention uses this DC voltage to determine the polarity of the FPLL synchronization at the receiver and to correct the polarity of the demodulated output signal, if required.

Objective of the Invention A main objective of the invention is to provide a novel FPLL system for a digital signal that has a pilot. Another object of the invention is to provide an improved demodulator for a digital signal having a pilot.

A further object of the invention is to provide a novel frequency synchronization indicator for a signal demodulated by an FPLL having a pilot.

BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the invention will become apparent after reading the following description in conjunction with the drawings, in which: FIGURE 1 is a simplified block diagram of a prior art FPLL demodulator; FIGURE 2 is a block diagram of an FPLL demodulator embodying the invention; FIGURES 3, 4 and 5 are waveforms shown at the points indicated in a block diagram of FIGURE 2; FIGURE 6 shows a frequency synchronization indicator of the invention; and FIGURE 7 shows waveforms at selected points in the circuit of FIGURE 6.

Description of the Preferred Modality Referring to the FPLL of the prior art of the FIGURE 1, a first multiplier 10 and a second multiplier 12 are each supplied with a common input signal and with the phase shifted demodulation signals of a phase shifter 14. The phase shifter 14 is driven by a controlled oscillator by voltage (VCO) 16 which in turn is driven by the output of an APC filter 18 that is supplied with the output of a third multiplier 20. Two low-pass filters 22 and 24 are connected to the outputs of the first and second multipliers 10 and 12, respectively. The low pass filter 22 supplies the demodulated signal to a signal processor. . 30 for further processing. The output of the low pass filter 22 is also supplied to a low pass filter SFC 26. The low pass filter 26 is coupled to a limiter 28, the output from which supplies an input of the third multiplier 20 ^ The other input of the third multiplier 20 is supplied from the low pass filter 24. The FPLL circuit of the prior art operates to demodulate the incoming signal and supply it to the signal processor 30. As is well known, the upper portion of the block diagram generally comprises an automatic frequency control circuit (AFC) and the lower portion comprises an automatic phase control circuit (APC). When the frequency synchronization between the VCO signal and the incoming signal occurs, the polarity of the demodulated signal that is supplied to the signal processor 30 may be positive or negative, depending on the phase relationships between the input signal and the output of the signal. demodulation of the phase shifter 14. In the circuit of FIGURE 1, no means are shown to compensate for the biphasic stability of the circuit and therefore the demodulated output can be of any polarity, i.e., positive or negative. In the circuit of FIGURE 2, the FPLL circuit of FIGURE 1 is essentially duplicated and the common elements are indicated by the same reference numbers. The output of the low pass filter 22 is also supplied, at a junction marked A, to another low pass filter circuit 32, which has different characteristics (e.g., lower bandwidth) than the low pass filter AFC 26. The output of the low pass filter 32 is marked B and is supplied to a limiter 34, the output of which is marked C. The limiter 34 is coupled to a polarity determining circuit 36 and to a signaling circuit. frequency synchronization 38. The frequency synchronization indicator circuit 38, in turn, is coupled to the polarity determination circuit 36 and controls its operation. The polarity determination circuit 36 has a solid line connection to a phase inverter 40 which is inserted between the input signal terminal and the first and second multipliers 10 and 12. The polarity determination circuit 36 also has a dotted line connection to a phase inverter (dotted line) 42 that is inserted between the low pass filter 22 and the signal processor 30. It should be noted that only the dotted line and solid line versions of the circuit are implemented. After synchronization of the FPLL, the output of the low pass filter 22 comprises a demodulated data signal and a DC voltage representing the pilot. This signal is applied to the low pass filter 32 and the limiter 34, which produces a DC voltage at the output of the limiter 34 representative of the polarity of the pilot. The output of limiter 34, as will be seen in relation to FIGS. 4 and 5, can alternate above and below the zero carrier level before synchronization and reaching a positive or negative level when frequency synchronization occurs. , depending on the synchronization phase of the bistable FPLL. The polarity determining circuit 36 determines the level of the demodulated pilot signal if the input signal or the demodulated output signal should be inverted in phase to supply a signal of predetermined polarity to the signal processor 30. Depending on the implementation of the circuit used, a method of post-processing or feedback may be used for the invention. In the solid line circuit including the phase inverter 40, the feedback method was used where the input signal is inverted when the polarity of the demodulated pilot signal indicates that the demodulated output signal will not have the predetermined polarity. On the other hand, the method of postal signaling indicated by the dotted line circuit that includes the inverter 42 will achieve the same result by inverting the polarity of the demodulated output signal before it is supplied to the signal processor 30. It should be noted that the circuit Polarity determination 36 is not activated until a synchronization condition has been determined by the frequency synchronizing indicator circuit 38. This occurs when the output of the limiter 34 becomes static (no change) for a period of time. In practice, if the output of the limiter does not change state for a predetermined period of time, it can be assumed that the FPLL is synchronized by frequency or very close to the frequency synchronization, ie, within the half-cycle synchronization interval of the PLL portion. of the circuit. Under any condition, the polarity of the demodulator output can be determined and corrected, if necessary. Greater confidence in frequency synchronization can be obtained with the use of a confidence counter to indicate that a sufficient number of consecutive predetermined intervals have occurred to ensure the condition of frequency synchronization. Alternatively, a very large predetermined interval may be used to verify the output of the limiter. For example, for a time interval of 1.0 milliseconds, it will be determined that a beat frequency of 500 Hz or more is an unsynchronized signal. The frequency synchronization detection scheme (which uses a small pilot) can be used in other FPLL applications where frequency synchronization must occur before the processing of another signal can take place. FIGURES 3, 4 and 5 represent waveforms of the signals present at points A, B and C, respectively, of the FPLL of FIGURE 2 during the reception of a level 8 digital signal VSB having a pilot component in phase of CD. The illustrations marked as Case (1) represent the condition of the synchronization of the FPLL of positive polarity, the illustrations marked as Case (2), the condition of the synchronization of the FPLL of negative polarity and the illustrations marked as Case 3, of synchronization of the frequency of the FPLL. For the case (3) (frequency synchronization), the signal and the data output of the LPF 22 (FIGURE 3) alternates above and below the carrier level of zero with an average value of zero. This results in a sinusoidal beat signal at the output of the LPF 32 (FIGURE 4) which corresponds to the difference to the frequency difference between the two signals applied to the multiplier 10. Therefore a corresponding square wave signal is generated in the output of limiter 34 (FIGURE 5). The square wave signal at the output of the limiter 34 indicates a frequency desynchronization condition of the FPLL and is detected by the frequency synchronizing indicator circuit 38 to deactivate the polarity determining circuit 36. Once the synchronization of the frequency, the demodulated data signal developed at the output of the AFC LPF 26 will assume the form of Case (1) or Case (2) of FIGURE 3. In the case (1) the average level of the signal of data is greater than the carrier level of zero and results in a positive DC voltage at the LPF 32 output (FIGURE 4). The output of the limiter 34 (FIGURE 5) is therefore a signal +1, which is detected by the frequency synchronizing indicator circuit 38 to activate the polarity determining circuit 36. The circuit 36, in turn , detects the +1 output of the limiter 34 to determine that the FPLL has reached positive polarity synchronization and generates an output control signal to apply to the inverter 40 or 42 keeping the inverter in its current state.

For the case (2) of FIGURE 3, the average level of the data signal at the output of the LPF 22 is lower than the carrier level of zero and therefore results in a negative DC voltage at the output of the LPF. 32 (FIGURE 4). The output of the limiter 34 (FIGURE 5) is therefore a signal -1 which is also detected by the frequency synchronizing indicator circuit 38 to activate the polarity determining circuit 36. The circuit 36, in this case, detects the -1 output of the limiter 34 to determine that the FPLL has reached negative polarity synchronization and generates an output control signal to apply to the inverter 40 or 42 to change the state of the inverter. That is, if the investor were not in their investment status, it would be commuted to their investment status and vice versa. The frequency synchronizing indicator circuit 38 of the invention is illustrated in greater detail in FIGS. 6 and 7. A portion of the FPLL of FIGURE 1 was reproduced. Specifically, the LPFs 22 and 24, the APC LPF 26, the limiter are shown. 28 and the third multiplier 20. The frequency synchronizing indicator circuit consists of a zero-crossing detector 50, a first latch 56, a timer 58 and a second latch 62. An optional confidence counter 60 is illustrated in dotted lines. The clock input of the second latch 62 is connected to a reset terminal of the first latch 56. In this way the output of the second latch 62 remains constant as long as it is synchronized or desynchronized. The zero crossing detector 50 includes a delay circuit 52 and an exclusive OR gate (XOR) 54. The input is taken from the output of the limiter 28 (marked F), which output also supplies the circuit for determining the 36. The combination of the delay 52 and the XOR 54 serves as a limit detector for the square wave output (which occurs during the frequency synchronization condition) of the limiter 28 and generates pulses corresponding to the limits of the square wave. This is illustrated in more detail in FIGURE 7. Waveform E in FIGURE 7 was taken at the input of limiter 28 and is a beat frequency signal that decreases in frequency as it approaches frequency synchronization. by the FPLL. In phase synchronization, the signal is converted to +1 or -1, depending on the synchronization phase of the FPLL. The waveform F, as mentioned, is the square wave produced by the limiter 28 of the waveform E. The boundaries of the square wave F correspond to the zero crossings of the beat frequency signal E. The shape The G wave is taken at the output of XOR 54 and is observed as a series of sharply defined pulses that correspond to the limits of the square wave F and thus occur at the zero crossings of the E waveform. The width of the impulses is determined by the delay of the delay 52 and is not critical. Returning to FIGURE 6, the pulses of the waveform G are stored in a first latch 56 and a timer 58 controls the sampling of the first latch 56 via the clock input and resets the first, latch 56 via the reset input. The first lock 56 can be conveniently arranged to produce a level "1" signal if zero crossings have not been sampled by the lock 56 in the time period set by the timer 58. That would be a control signal indicating that it has Frequency synchronization occurred since no crossings by zero have been found in the selected period of time. The period of time would be more than prolonged, in the order of a second, in this modality. If, on the other hand, one or more limits have been sampled by the latch 56 within the set time period, a control signal will be produced indicating a condition of frequency desynchronization at the output of the latch. The output of the control signal of the first latch 56 is supplied, through the second latch 62, to the polarity determining circuit 36, which observes the polarity of the signal received from the output of the limiter 28. In response to the synchronization detection of the frequency, if the polarity is correct, no changes are made. If, however, the polarity is incorrect, the polarity determining circuit 36 produces an appropriate signal for the phase inverter (40 or 42) to produce a data output of the proper polarity. In the case where the optional confidence counter 60 is employed, the output signal from the first latch 56, which would be sampled on a more frequent basis, is supplied, via the second latch 62, to the confidence counter 60. Each time If no crosses are found by zero in the selected sampling time period, the confidence counter would increase until a predetermined number of "no crossings by zero" has been reached. When that occurs (which corresponds to a CD output of the limiter 28), the confidence counter could supply a synchronization indication signal to the polarity determination circuit 36 and the operation would proceed as described above. What has been described is a novel FPLL frequency synchronization indicating circuit for a digital signal having a pilot. It is recognized that numerous changes in the described embodiment of the invention will be apparent to those skilled in the art without departing from its true spirit and scope. The invention is limited only by what is defined in the claims.

It is noted that in relation to this date, the best method known by the applicant to carry out the aforementioned invention, is the conventional one for the manufacture of the objects to which it relates.

Claims (10)

CLAIMS Having described the invention as above, property is claimed as contained in the following:

1. A frequency synchronization indicator for use with an FPLL demodulator for demodulating a received signal having a pilot signal, characterized in that the synchronization indicator includes means for detecting zero crossings of the demodulated pilot signal, means for developing a control signal in response to zero crossing detection means, and means responsive to the control signal to produce a frequency synchronization indication. The frequency synchronization indicator according to claim 1, characterized in that the means for detecting zero crossings include means for detecting one or more zero crossings of the demodulated pilot signal during a selected time interval. 3. The frequency synchronization indicator according to claim 2, characterized in that the zero crossing detection means includes confidence counter means for determining when the control signal is substantially DC (Direct Current). 4. The frequency synchronization indicator according to claim 2, characterized in that the FPLL demodulator develops a square wave signal of beat frequency during frequency synchronization and characterized in that in addition the means for detecting zero crossings include means for converting the square wave beat frequency signal to pulses, means for retaining the pulses, and means for sampling the output of the retaining means. 5. The frequency synchronization indicator according to claim 4, characterized in that the reliable counter means is coupled to the sampling means for generating the control signal when zero crossings have not been detected for a predetermined number of samples. 6. The frequency synchronization indicator according to claim 4, characterized in that the conversion means include an exclusive OR gate and a delay circuit, the square wave signal of beat frequency is supplied to the exclusive OR gate directly and through the delay circuit. 7. An FPLL demodulator characterized by means for demodulating an input signal having a pilot signal, the demodulation means includes means for generating a pair of oscillator signals shifted by phase at 90 ° to produce a limited output signal corresponding to the demodulated pilot signal, zero crossing detection means receiving the limited output signal and determining the zero crossings in it, sampling means to determine if one or more of the zero crossings have occurred in a time interval predetermined, and means responsive to the sampling means to produce a synchronization signal indicative of the frequency synchronization of the FPLL demodulator. The FPLL demodulator according to claim 7, characterized in that the zero crossing detection means includes means for generating pulses corresponding to zero crossings, and wherein the sampling means includes retention means for temporarily storing impulses generated by means of detection of crosses by zero. The FPLL demodulator according to claim 8, characterized in that the pulse generating means comprise a delay circuit and an exclusive OR gate, the output signal of the limiter is supplied to the exclusive OR gate directly and through the delay circuit . The FPLL demodulator according to claim 8, characterized in that the means that produce the synchronization signal includes reliable counters for determining the pulses when an output signal limited substantially by DC is being received.