MXPA96005068A - Clock resynchronization apparatus with stages deretraso in casc - Google Patents

Abstract

The present invention relates to integrated clock resynchronization apparatus, comprising: a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit and responding to a clock input signal to provide a plurality of delayed clock signals in respective taps; a selection circuit responsive to a timing signal supplied thereto, for coupling one of the selected taps to an output to provide a delayed clock output signal that is aligned at the edge with the synchronization signal, and where the number of delay elements among some derivations varies, each delay element of the delay line is of a specific nominal delay, the delay elements are arranged on the delay line to form a delay element. distribution of delay elements where there are fewer derivations than elements of delay or, the distribution of delay elements between the derivations is selected to minimize the number of derivations required to provide a given minimum delay resolution and a minimum total delay given for the delay line, and where the minimum total delay is so minus one period of the clock signal enters

Description

CLOCK RESYNCHRONIZATION APPARATUS WITH DELAYED STAGES IN CASCADE DESCRIPTION OF THE INVENTION This invention relates to delay circuits and particularly to delay circuits with cascade delay stages and to a selector for resynchronizing clock signals. Lps delay circuits employing cascade delay stages and a selection circuit for resynchronizing a clock signal with a synchronization signal are well known and widely used, for example, in a video signal synchronization circuit. An example is described by illis et al., In the U.A. 4992874 entitled "Method and Apparatus for Correcting Synchronization Errors as for a Multiple Image Representation" (Method and Apparatus for Correcting Timing Errors as for a Multi-picture Display), issued on February 12, 1991. Willis and others describe a system of image distortion correction for a television imager with image-in-picture (PIP) processing. An element of a mode of the PI P receiver of Willis and others includes a clock phase change circuit, which resynchronizes a locked sample clock to break the main image signal with a horizontal synchronization signal derived from the processing circuit of image representation. The present invention is directed to provide certain improvements in the clock resynchronization circuit system of the general type described by Willis et al. To facilitate the construction of the resynchronization circuit system in an integrated circuit using standard semiconductor processing techniques. In order to understand the nature of the problems solved by the present invention, it is useful to first consider a modality of the resynchronization circuit of Willis and others, in some detail. Up to now, Figure 1 of the present one, marked with "Prior Art" has been drawn based on the patent of Willis et al. The clock resynchronization apparatus 100 of FIG. 1 includes an input terminal 102 for receiving a main clock input signal MCK that is to be resyncronized or "edge aligned" with a horizontal synchronization signal HS. The main clock input signal MCK is coupled via the ducts 104 to the output of a derived delay line 130 comprising delay elements 15, 1 1 - 15 15. The taps of the delay line T1 -T15 together with the master clock input signal MCK not delayed are applied via the link 1 12 and the conductor 104, respectively, to a memory unit 106 comprising fifteen oscillators of the "clock" type. D ". All the oscillators in the memory unit 106 are timed simultaneously by the leading edge of a horizontal synchronization signal HS applied to the input terminal 1 14. As a result, the fifteen oscillators in the memory 106 store what can be thought to be a "snapshot" or "image" of all delay line derivation values at the time the horizontal synchronization pulse arrives. Since there are fifteen delays of at least 5 nano-seconds each, the stored derivation values represent samples of a complete cycle (v. Gr., 70 nano-seconds, assumed by NTSC) of the MCK clock signal. at the time of the arrival of the horizontal synchronization signal. By comparing the fifteen derivation values stored in the oscillators 106, it can be determined which derivation output signal has its edge closest to the leading edge of the horizontal synchronization HS. This identification is made by the multiple-selection logic unit 108 which receives the fifteen stored derivation values of the memory unit 106 via the bar 18 of the driver 15. Of the fifteen input bypass delays, the unit 108 provides a signal output on the conductor 16 of the bar 120, which identifies which of the fifteen delayed signals in the taps T1 ^ T15 or the input signal (not delayed) has a border or transition that is very close to the edge of the synchronization signal horizontal HS. The nearest bypass signal, after identification by the logic unit 108, it is supplied via the conductor 16 of the bar 120 to a multiple selection switch 1 10. The switch 1 10 then selects one of the fifteen (delayed) bypass signals or the input (not delayed) as a YCK output signal and applies this signal to output terminal 1 16 for the rest of the horizontal line.

In the above manner, the MCK input master clock signal is delayed by the derivation of the selection logic unit 106 that is closest to the leading edge of horizontal synchronization and this derivation is used to delay all of the following master clock signals for the rest of the horizontal line. When the next horizontal line begins, the edge of the synchronization again locks all the derivation delay data in the memory 106 and the cycle is repeated. Accordingly, the master clock signal MCK is changed in the phase by the selected derivation delay to produce the phase shift output clock YCK which is aligned at the edge with the horizontal synchronization signal HS. The present invention is directed to a problem in the resynchronization apparatus of the type described, which refers to variations in the propagation delay of the delay elements and the propagation delay of gate transitions in the logic unit of the device. multiple selection 108 from one integrated circuit to another Variations in propagation delay are important as they can affect a number of resynchronization parameters, such as delay numbers and derivations, and the choice of customary cell manufacturing techniques or Normally, which in turn can also affect the performance and costs of the terminated circuits.More directly, in the previous description of the known resynchronization circuit, there are a total of 15 derivations and the master clock period was 70 nano- This period value is based on a normal assumed NTSC signal analyzed at a rate of four times the subpor (4Fsc) In order to provide a full cycle (70 nano-seconds) of delay for the MCK master clock, the delay line must provide a delay, which, at a minimum, is at a Excess of 70 nano-seconds. For 15 derivations, a delay of 5 nano-seconds per element of delay will provide a minimum total delay time of 75 nano-seconds, which satisfies the minimum requirement of total delay for the line. Another factor that affects the choice of derivation delay is the visual resolution of the human eye. It has been found that a delay resolution of 10 nano-seconds or finer is necessary to make border variations of vertical lines essentially imperceptible. The delay of 5 nano-seconds is more appropriate in this regard. If a maximum delay of 10 nano-seconds is assumed, based on the capacity of visual perception and a minimum delay of 5 nano-seconds per element for fifteen elements to provide the total minimum delay based on the master clock period, then the " Maximum extension of the delay values is in a two-to-one ratio (2: 1). The resynchronization circuits have been constructed using a semiconductor procedure with a propagation delay from batch to batch of two-to-one variations for delay elements. However, this 2: 1 ratio is a relatively close tolerance for processing with normal cell delay devices. To satisfy all the criteria discussed above, it has so far been found necessary to use "cells" (elements) of custom design delay to obtain a variation of delay or "extension", which does not exceed a ratio of 2: 1. By ordinarily designing a delay element in a semiconductor process, the variation of chip-to-chip delays can be reduced by a factor of approximately two-to-one (2: 1). On the other hand, there is a clear cost advantage in using normal cell delay elements, although the "extension" of the chip-to-phip delay can be much broader, such as a four-to-one ratio (4: 1). ) of expected delays at the minimum of batch-to-batch integrated circuits.

Another problem in implementing the known resynchronization circuit relates to the gate propagation delay in the multiple selection switch 108. Evoke that the logic unit 108 must make an identification of which the bypass signal is closest to the signal edge of the receiver. synchronization. If a delay extension of 4: 1 is chosen, then the maximum delay per derivation will be 10 nano-seconds (the threshold of perception) and the minimum delay will be 2.5 nano-seconds. For delayed element delays of 2.5 nano-seconds, 30 delays will be required to satisfy the requirement that the total minimum delay be greater than the clock period (>; 70nS). But if there are 30 delays, there must also be 30 inputs to the logical selection unit 108 and this logic unit employs serial or "carry" transmission processing. The difficulty is if the total gate propagation delay time in the selection logic unit 108 through 30 stages exceeds the master clock period, 70nS, then the selection logic unit 108 may fail to identify the clock edge. MCK closest and fails to complete all the processing of the 30 derivation signals within one clock cycle. The present invention is directed to satisfy the need for a clock resynchronization apparatus suitable for construction in an integrated circuit form, with delay elements that may exhibit relatively broad propagation delay variations, such as four-to-one . The delay apparatus modeling the invention comprises a cascade connection of a plurality of delay elements formed in an integrated circuit and responding to a clock input signal to provide a plurality of delayed clock signals in respective branches. A selection circuit, responsive to a synchronization signal supplied thereto, couples a selected branch to an output to provide a delayed clock output signal that is aligned at the edge with the synchronization signal. The number of delay elements among the selected leads varies. The invention is illustrated in the accompanying drawings, wherein; Figure 1 is a block diagram of a clock resynchronization apparatus, known in the prior art; Figure 2 is a block diagram of a clock resynchronization apparatus, which modalizes the invention; Figures 3A, 3B and 3C are detailed timing diagrams illustrating certain aspects of operation of the clock resynchronization apparatus of Figure 2; Figure 4 is a table of comparative normalized delay distributions for delay elements in the example of the invention of Figure 2; Figure 5 is a block diagram illustrating a modification of the apparatus of Figure 2; and Figure 6 is a logic diagram illustrating the derivation selection circuit suitable for use in the example of Figure 2. The clock resynchronization apparatus 200 of Figure 2, which modalizes the invention, is designed for construction in a form of integrated circuit with conventional "normal cell" delay elements, which can exhibit a batch-to-batch delay variation of up to four-to-one (4: 1) ratio without requiring as many derivations as those that could otherwise be required if the delay line was derived in each of the 29 elements of delay. This aspect presents the advantage of the fact that the only time the most right (ie the last) derivation can be selected is when the delay of its element is substantially less than the upper limit of 10 nano-seconds of the perception visual. This principle allows the normal delay by derivation to be geometrically increased along the line of delay and still ensures that the worst delay by derivation is less than the requirement of 10 nano-seconds. In fact, how it will be explained, the distribution of delay elements by derivation is not simply geometric, but includes a linear delay region and a progressive delay region. Detailed explanations of how to determine the delay distributions are discussed below to Figure 4. Evoke that the primary advantage of reducing the number of derivations is to reduce the number of inputs to the logical selection unit 8 of derivation. In this specific case, there is a reduction of 28 leads for a line of linear delay to 19 leads for a line of progressive delay. The logical unit of selection is a structure of type of carry (shown in detail in Figure 5) and of this form has a propagation time proportional to the number of entries. Must be fixed in less than one period (70 nSeg.) Of MCK master clock and the use of graduated or progressive derivation distributions, according to the invention, is an effective way to satisfy this requirement. In more detail, the clock resynchronization apparatus 200 of Figure 2 includes an input terminal 2 for receiving a main clock input signal MCK to be resynchronized with respect to a horizontal synchronization signal HS applied to an input terminal 14. The main clock input signal MCK is coupled via the driver 4 to the input of a derived delay line 30 comprising 29 delay elements? 1 -? 29. The delay elements are derived at 19 points to provide 19 delayed derivation signals (T1 -T19), which have a particular delay distribution, which is discussed below. The delayed bypass signals, together with the main clock input signal MCK not delayed, are applied via the bar 12 and the conductor 4, respectively, to a memory unit 6 comprising 19"D" or "type" oscillators. data". All the oscillators in the memory unit 106 are timed simultaneously by the leading edge of the horizontal input signal HS at the input terminal 14. As a result, the 19 oscillators in the memory 6 store what is thought to be a "snapshot". ", an" image ", or a waveform" profile "of a complete cycle of the master clock signal MCK on the delay line 30 taken at the time the synchronization signal HS arrives. The "snapshot" of the master clock signal is illustrated in Figure 3A by the waveforms TO to T6. The waveform T0 is the MCK master clock applied to the delay line input 30. The other waveforms correspond to the signals in the T1-T6 leads, respectively. Of course, there are a total of 19 derivation waveforms but only six are shown to simplify the drawing.

The vertical dotted line in Figures 3A and 3B is aligned to the horizontal synchronization transition and identifies all the derivation values (v. Gr, binary one or binary zero) that are stored in memory 8 at the time of the transition of horizontal synchronization signal 300. By comparing the 19 derivation values stored in memory 6, it can be determined which derivation is closest to the leading edge of the horizontal synchronization HS. This identification is made by means of the derivation selection logic unit to which it receives the 19 stored derivation values of the memory unit 6 via the bar 18. The nearest derivation in Figure 3 is the derivation T3 (in bold) which corresponds to the MCK master clock signal delayed by 3 delay elements. Once the nearest branch has been identified, the branch selection logic unit 8 sends a signal on one of the conductors of the bar 21 to the multi-switch 10. This causes the multiple switch 10 to connect the branch T3 to the output terminal 1 16. This is illustrated by the signal waveform YCK shown in Figure 3C, which shows that the leading edge of the resynchronized clock signal YCK is aligned with the leading edge of the horizontal synchronization signal HS and the same signal corresponds to the MCK master clock signal delayed by three delay elements. The area before the transition of the horizontal synchronization is scratched and this means that the previous phase of the YCK signal is not of interest. This follows since no data from the previous line is necessary to determine the delay of the current line. The delays, in other words, are determined again on a line-by-line basis and thus the delay of the previous line is not of consequence to determine the delay of the current line. To summarize up to this point, the master clock signal MCK is delayed by the selected tap on the input line 30 by the selection logic unit 6 of the tap data stored in the memory 106 and this tap is connected to the set terminal. output 1 16 by the multiple switch 10 thus delaying all the following master clock signals for the remainder of the horizontal line. When the next horizontal line begins, the edge of the horizontal synchronization again locks all the derivation delay data in the memory 106 and the cycle repeats. Accordingly, the master clock signal MCK is changed in the phase by the selected bypass delay to produce the changed phase output clock YCK 304, i.e., the edge aligned with the horizontal synchronization signal HS. All the following clock cycles for the remainder of a horizontal line are thus synchronized with the horizontal synchronization signal HS. When the next horizontal signal appears, the procedure is repeated with the output clock YCK being synchronized with the synchronization signal HS, so that the resynchronized clock signal YCK is updated for each horizontal line. The delay line 30, in Figure 2, is intended to be manufactured with delay elements, which may have a delay variation, from batch to batch, of, four-to-one (4: 1) and specifically of a minimum from 2.5 nano-seconds to a maximum of 10 nano-seconds. By the term variation from batch to batch, it is meant that in a production operation of clock resynchronization circuits \ all delays can be 2.5 nano-Segments and in another production operation, all delays can be of 10 nano-seconds. On the line of * delay 30, the total number of delay elements is increased to 29, thus providing a maximum delay of 72.5 nano-seconds for the entire line, the worst condition case of all the elements of delay being of 2.5 nano-seconds This delay of 72.5 nano-seconds is greater than the period of the master clock, which is 70 nano-seconds (NTSC signal submerged with timing to four times the color subtransmitter), and therefore covers a wide scale of relationships between the MCK main clock and the leading edge of the horizontal sync signal HS. The "delay distribution" of the delay elements by derivation is shown in the example of Figure 2, where it can be seen that there are 29 delay elements and only 19 leads, and the derivation distribution is not uniform. The first 13 derivations, for example, are "separated" to a delay element, the following 3 derivations are separated by two delay elements, the next two derivations are separated by three delay elements and the last derivation is separated from four elements d delay of the preceding derivation 18. This distribution provides a derivation resolution of at least ten nano seconds for variations of delay element on a 4: 1 scale. Figure 4 provides a tabular presentation of a delay distribution of Figure 2, and also for three other cases. In Figure 4, the first column is the derivation number for the delay line 30. The second column labeled "elements of uniform delay" illustrates those for a delay line with a delay element between each derivation, the number total of required derivations could be 28 to provide a minimum total delay of 70 nano-seconds. The column labeled "unit delay elements" is a list of the elements by derivation, for example, of Figure 2. As shown, the number of derivations is reduced to 19 for a minimum total delay of 72.5 nano-seconds. This is a significant reduction compared to the 28 derivations required for a linear delay line. The column marked with half of the unit delay elements is an example of a delay distribution, which can be used if you have delay elements of 1.25 micro-seconds (half of 2.5 micro-seconds). As shown, there is another reduction of two derivations, but more delay elements are required. The last column in the table in Figure 4 illustrates the derivation requirements, if you have a normal set of cells containing continuously adjustable delay elements. This case also represents the absolute minimum number of derivations for a resynchronization circuit that satisfies the specific requirements of a total delay, delay resolution, extension of delay, etc. , of the illustrated modality. As you can see, the continuous case is approaching a minimum derivation delay of 4.00 units in only 16 derivations. This is better than the semitic example, and 3 times better than the unitary example. However, when considering the construction of unit delays or the need for extra delays in the semi-annual example, the clear preference is the simple unit version of Figure 2. Calculating specific delays by derivation is not a simple task, but it can be easily understood by considering the following equations, which govern the distribution of delays and some associated examples. First, consideration will be given to a calculation of the derivation delays for the case of continuous delay. The discrete cases of delay, discussed later, are essentially whole extensions of the continuous case. In the continuous case, the first seven derivations must be equal to a "normal delay element". Since the broader delay element may not be more than 10 nano-seconds, to satisfy the visual resolution requirements previously discussed, and since the total delay must be equal to 70 nano-seconds, at least 7 elements of delay of 10 nano-seconds, each one, are required to produce the minimum total of 70 nano-seconds and a resolution of uniform delay, from derivation to derivation, of 10 nano-seconds. Therefore, in the "continuous delay" column, in Figure 4, the first seven derivations are listed as 1.00, given one. All listed values are normalized against what is called "normal delay element", which can be any value between 2.5 and 10 nano-seconds, depending on the manufacturing procedure. The actual delay is then obtained by multiplying the "normal delay element" value by the normalized value. The next derivation, ta derivation number 8, and all the following derivations, are calculated by the following relationships for an extension of 4: 1, a maximum derivation difference of 10 nano-seconds, and a total delay of at least 70 nano -seconds (the reciprocal movement of the MCK master clock). First, for the Nth derivation, it is observed that: (S + Xn) T = 70 ns (1) Xn T = 10 ns (2) Xn = (1/6) (S) = 0.16666 S (3) In equations 1 -3 above: S is the sum of the normal delays from all stages preceding the Nth stage (v. gr., stages from N to N 1). T is the delay by "normal delay element". Xn is the normalized incremental delay (eg, it is the incremental delay divided by the delay by "element of normal delay") for a given stage "n" for the case where the elements of delay can be varied on a basis continuous (Figure 4, column on the right) 10, is a constant of 10 nano-seconds that corresponds to the minimum acceptable resolution and, 70, is a constant of nano-seconds that corresponds to the minimum total delay for the entire line . This is equal to the reciprocal movement of the MCK master clock signal. Equation (1), above, indicates that the sum of the actual delay and all previous delays must be equal to a minimum value of 70 nano-seconds, which is the MCK master clock period. Equation (2) defines the normalized incremental delay in terms of minimum acceptable resolution (eg, 10 nano-seconds). Combining equations (1) and (2), above, and solving for Xn, equation (3) is obtained, which provides a value that is the normalized incremental delay for the Nth derivation in a progressively calculated delay line. As an example of use of equation (3), the normalized incremental delay value for the Nth stage is determined by taking a sixth of the sum of the normalized delays of all the previous stages (N-1). In any delay line for the above specifications, there must be at least seven unit value delays, since the delays must be as much as 10 nano-seconds, thus calculating the total delay for the delay line. In this way, each of the first seven etgpas must have a normalized incremental delay of "1". For stage 8, the sum of the previous stages is 7, so for stage 8, the normalized incremental delay is ("X") 0.16666 (7), which is equal to 1.16666. This is shown as the entry in the "continuous" column in Figure 4 for derivation 8. Adding the normalized incremental delay (1.1666) for derivation 7 to the previous seven derivations gives a total of 8.1666 for the sum of all the previous normalized incremental delays. Dividing this (8.1666) by 6, gives the normalized incremental delay of 1 .361 1 for 9a. derivation. Repeating this procedure, the normalized incremental delays can be calculated for all the steps, as shown in Figure 4. The calculation of the discrete values of the normalized incremental delays is similar to the calculation of the continuous values, except that the normalized incremental value for any stage it is not added to the previous sum, unless it is an integer. As an example, starting with step 8, the normalized incremental values are 1.1666, 1.250, 1.500; 1.6666; and 1 .81 1 for leads 8-12. None of these are integers. None is added when equation (3) is applied, so that derivations 1 - 12 all have normalized incremental values of 1, the sum S is equal to 12. Derivation 13 is the first derivation in this example, which has a normalized incremental value that is a whole step. Specifically, for derivation 13, the sum of all previous normalized values is 12 and 12 divided by 6 equals 2. Therefore, there are two delay elements between derivation 13 and the next derivation and the incremental derivation value Normalized (to be used with lead 14) will be advanced by "2". Finally, the normalized incremental values increase in steps of "3" and finally, the last step is a value of "4" (representing that 4 stages of 2.5 nano-seconds each are required). Figure 5 is an example of a delay distribution satisfied by the use of "average delay" elements of 1.25 nano-seconds, each. These middle elements implement the distribution in Figure 4 for the middle unit column. As shown, only 17 leads are needed (2 less than for the unit example), but 49 delays are used. As a practical way, few delays can be used, if delays of both 2.5 and 1.25 nano-seconds can be formed on the integrated circuit. Figure 6 illustrates details of the appropriate logic circuit to implement the resynchronization apparatus of Figure 2 Oscillators, the selection circuit and the multiple switch circuits are similar for each derivation, so only few stages are shown to simplify the drawing . The exceptions are the first and last stages, which provide feedback to stop the selection procedure after the previous edge of the synchronization is reached. Essentially 6 oscillators "D", the logical unit of mui selection. 8 and switch 10 is shown in the aforementioned patent of Willis et al. No. 4, 992, 874, and only a brief description will be given. The total operation of the circuit is exactly as discussed previously in the example of Figure 2 and related figures 3 and 4. In response to a positive transition of the MCK master clock signal, instantaneous samples of each of the different phases of the MCK signal are stored in the respective D-type oscillators (610,620, 630,640) of the memory 6. the total delay provided by the delay line 30 approaches a period of the MCK master clock signal, the values stored in these oscillators represent a "snapshot" of all phases of the MCK clock signal in the different derivations, taken in the transition of the HS synchronization signal. If this "snapshot" includes a positive transition of the master clock signal, one of the oscillators, for example 620, will have a logical output signal of one, and the next successive oscillator, 630, will have a logical output signal of zero. In this case, all the input signals to an AND gate 634 of the logic selection unit 8 of derivation will be logic of one. In this case, the gate output signal AND 634 will capacitate the clock phase signal provided by the lead 18 to pass through an AN D gate 638 and an OR gate 660 (at the multiple switch 10), to As the signal is output from the resynchronization apparatus and the branch 18 remain connected to the output terminal 16 for the remainder of the horizontal line interval until the next synchronization pulse appears. When the logical levels of the derivation or "snapshot" stored in the memory 6 include more than one transition, inhibiting the circuit system, which includes the inverted 616, 636, 646, and 656, only the signal phase is allowed. clock, corresponding to the first transition, is selected as the delayed clock output signal YCK. When the "snapshot" includes only a transition that goes negative, or when the sample values held in the oscillators are all logical to one, indicating that there is no captured transition, the phase of the clock signal provided by the delay element 29 in branch 19, it is selected as the phase aligned output signal YCK. This selection by means of the "pseudo-etßpa" 655. Finally, when the "snapshot" does not imply any transition, but the values maintained in the various oscillators are all logical to zero, the MCK master clock signal is selected as the phase aligned output signal YCK by the action of the AND gates 614 and 618 and an inverter 616.

Claims (7)

1 .- An integrated clock resynchronization device, characterized by: a delay line (30) comprising a cascade connection of a plurality (T1 -T19) of delay elements that respond to a clock input signal for providing a plurality of delayed clock signals to respective branches; a selection circuit (6), responsive to a synchronization signal (HS) supplied thereto, for coupling one of the selected leads to an output to provide a delayed clock output signal (YCK) that is aligned on the edge with the synchronization signal; and where: the number of delay elements, among some derivations, varies.

2. The apparatus of claim 1, further characterized in that: the number of delay elements, between the branches, is constant for a first group (T1 -T13) of leads and is graduated for a second group (T14-T16; T17-T18; T19) of the leads.

3. The apparatus of claim 2, further characterized in that: said first group of leads are separated to a delay element for a given number of delay elements in said cascade; and said second group of derivations are separated to at least two delay elements from a predetermined number of said derivations.

4. The apparatus of any of claims 1, 2, or 3, further characterized in that: the distribution of the delay elements between the branches is selected to minimize the number of derivations required to provide a resolution of the minimum delay , for the resynchronized clock output signal and a minimum total delay given for said delay line.

5. The apparatus of any of claims 1, 2, or 3, further characterized in that: said delay elements in a given integrated circuit are of uniform delay, but exhibit a scale of variations of delay from one integrated circuit to another that it can vary on a predetermined scale; and the distribution of delay elements between the derivations is selected to minimize the number of derivations required to provide a given minimum delay resolution and a minimum total delay given for said delay line.

6. The apparatus of any of claims 1, or 2, further characterized in that: the distribution of delay elements between the derivations is selected to minimize the number of derivations required to provide a given minimum delay resolution and a delay minimum total given for said line of delay; and wherein: said minimum total delay is at least one period of said input clock signal.

7. The apparatus of any of claims 1, or 2, further characterized in that: the distribution of delay elements between the leads is selected to minimize the number of leads required to provide a given minimum delay resolution and a minimum total delay gives or for delay line; and where: said resolution of minimum delay is? e approximately 10 micro-seconds. 8 - The apparatus of any of claims 1, or 2, further characterized in that: the distribution of the delay items between the derivations is selected to minimize the number of derivations required to provide a given minimum delay resolution and a minimum total delay given for said line of delay; and wherein: said minimum total delay is at least one period of said input clock signal; and wherein: said minimum delay resolution is approximately 10 micro-seconds. 9. The apparatus of any of claims 1, or 2, further characterized in that: the delay elements within a given integrated circuit are of a uniform delay; and wherein: the delay elements of an integrated circuit may differ in delay from those of another integrated delay circuit by a factor greater than two-to-one. 10.- A method to resynchronize the video clock input signal to align with a horizontal synchronization (HS) signal, characterized in that it comprises the steps of: applying said video input clock signal to an integrated circuit derived to a delay line to produce a plurality of progressively delayed clock signals to respective output branches of said delay line; coupling the leads to an output terminal under a given transition of horizontal synchronization signal to provide a resynchronized video output clock signal, which is aligned at the edge with said synchronization signal; and selecting a non-linear delay time distribution by derivation to minimize the number of derivations required to provide a given minimum delay resolution of the resynchronized video clock output signal and to provide a given minimum total delay for said line of derived delay. 1 - The method of claim 10, further characterized in that the step of selecting said predetermined non-linear distribution of delay time by derivation comprises: distributing a first group of delay elements in the delay line to provide a constant delay by derivation and distribute a second group of elements of delay in said line of delay to provide progressively greater delays by derivation. 12. The method of claim 10, further characterized in that: it selects, as said resolution of minimum delay, a time of approximately 10 micro-seconds; and selects, as said minimum total delay for said delay line, a time substantially equal to the period of said input clock signal. SUMMARY A video clock input signal (MCK) is applied to a delay line (30) comprising a cascade connection of a plurality (T1 -T19) of delay elements to provide a plurality of delayed clock signals eh derivations respective (T1 -T15) of the delay line. A selection circuit (6), which responds to a horizontal synchronization signal (HS) supplied thereto, couples a selected branch to an output to provide a delayed output clock signal (YCK) that is aligned at the edge with the synchronization signal (HS). To reduce the number of derivations required to provide a given minimum delay step resolution and a minimum total delay for the delay elements, which may vary in delay from one circuit to another, the leads are separated to a separate element of the circuit. a first group (T1 -T13) of the delay elements and are separated to more than one separate element of at least (T13-T16; T17-T18; T19) a second group of elements.