OUTPUT STAGE OF AN ADEQUATE OPERATIONAL AMPLIFIER FOR MOUNTING ON A SUBSTRATE AND METHOD
AMPLIFICATION WITH THE SAME Background of the Invention 1. Field of the Invention The present invention relates generally to amplifiers and more specifically to output stages of operational amplifiers. 2. Description of the Related Art Generally, an operational amplifier (amp op) is used in many applications including, but not limited to, radiotelephones. In fact, current radiotelephones include multiple operational amplifiers to increase the signal strength in both the receiver and the transmitter. Typically, such operational amplifiers are mounted, along with other circuitry, on a substrate of an integrated circuit (IC). Since radiotelephones become smaller and more portable, there is a growing need for operational amplifiers to operate efficiently with low power supply voltages. The operational amplifiers consist of an input stage, an intermediate stage and an exit stage. When the operational amplifier is mounted on an IC in a signal output thereof, it is necessary that the output stage of the operational amplifier provide a low impedance output. The low impedance output prevents the rest of the circuit mounted on the IC from becoming unstable after large amounts of capacitance provided by other ICs or other directly coupled components. Unfortunately, many of the output stages of existing operational amplifiers, including those with the ability to fluctuate from track to track, exhibit a high output impedance. Figure 1 is a schematic illustration of a known low impedance output stage for an operational amplifier comprising a complementary transmitter (or source) buffer 100. The buffer 100 is energized by a first voltage supply path ( + VBB) 102 and a second supply voltage path 104. The buffer 100 includes an input 106 for receiving an input voltage 105. The input 106 is coupled to intermediate storage devices, first and second, 108, 110 through of respective, first and second branch devices, 112, 114. In response to the input voltage 105, the first and second intermediate storage devices 108, 110 provide an output voltage 115 and an output current 117, so collectively an output signal, in an output 116 coupled to it. The output signal is capable of driving a load, such as another IC,
(not shown) which is coupled to the output 116 and energized in a similar manner by the first and second supply voltage pathways 102, 104. FIG. 2 is an illustration in graphical form of a known voltage transfer characteristic. 200 of the buffer 100 of FIG. 1. In response to the input voltage 105, the first and second buffer storage devices 108, 110 alternate their operation to provide the output signal. As the input voltage 105 exceeds + VBB / 2, as designated by the portion 202 of the transfer characteristic 200, the output current 117 is emitted basically to the output 116 of Figure 1 by the first storage device intermediate 108. As the input voltage 105 drops below + VBB / 2, as designated by the portion 204 of the transfer characteristic 200, the output current 117 descends basically from the output 116 via the second output device. intermediate storage 110. The first and second bypass devices 112, 114 ensure that the intermediate storage devices, first and second, 108, 110, respectively, remain on to prevent crossover distortion as - -
that the input voltage 105 approximately equals, or passes through, + VBB / 2, as designated by point 206 in the transfer characteristic 200. Due to the electrical limitations of the base emitter junction of the bipolar junction transistors comprising the first and second bypass devices 108, 110, the buffer 100 is unable to provide the output signal and direct the load over a maximum voltage range 208. The maximum voltage range 208 is defined by the difference between supply voltage paths, first and second 102, 104 and designated 0V to + VBB. In fact, the buffer 100 is unable to provide the output signal when the input voltage 105 is within a diode drop of any first or second voltage supply path, 102, 104. A common diode drop it is known as the voltage drop between the base and the emitter of a bipolar junction transistor. Accordingly, the buffer 100 is effectively limited to the operation in an intermediate voltage range 210 defined by the difference in the first supply voltage path 102 lower than the diode drop and the second supply voltage path 104 less than another diode drop. Assuming that the diode drop is about 0.8V, the intermediate voltage range 210 extends from about 0.8V to about + VBB-0.8V as shown in Figure 2. In low power applications, the loss of the range of operation, or the lack of ability to fluctuate from track to track, due to the two diode drops, creates a substantial limitation. For example, if the first supply voltage path 102 is 3V and the second voltage supply path 104 is OV as shown, the maximum voltage range 208 becomes 3V and the intermediate voltage range 210 becomes of approximately 1.4V. In such a case, the buffer 100 would be unable to provide the output signal and direct the load for more than half (approximately 1.6V) of the maximum voltage range of 3V 208. Therefore, what is needed is a step of output for an operational amplifier that has the ability to fluctuate from track to track in order to be suitable for use in a low voltage application and having a low output impedance in order to be suitable for mounting on the output of an IC. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a known output stage of an operational amplifier; Figure 2 is a graphical illustration of a known voltage transfer characteristic of the output stage of Figure 1; Figure 3 is an illustration in block diagram form of a radio frequency communication system employing a radiotelephone; Figure 4 is an illustration in block diagram form, with limited detail, of a synthesizer of the radiotelephone of Figure 3, the synthesizer employing an operational amplifier; Figure 5 is a schematic illustration of an output stage of the operational amplifier of Figure 4; Figure 6 is a graphical illustration of a voltage transfer characteristic of the output stage of Figure 5; Figure 7 is a schematic illustration of an alternate output stage of the operational amplifier of Figure 4; and Figure 8 is an illustration in flowchart form of a method for applying an input voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An output stage for an operational amplifier energized by a first supply voltage path and a second supply voltage path includes a buffer and a current amplifier for amplifying an input voltage to a signal of low impedance output. The buffer amplifies the input voltage to the output signal amplified when the input voltage is within a maximum voltage range defined by a voltage difference between the first supply voltage path and the second supply voltage path. The current amplifier helps the buffer to amplify the input voltage to the amplified output signal when the input voltage is outside the intermediate voltage range but within the maximum voltage range. Figure 3 is an illustration in block diagram form of a radio frequency communication system 300 in which a transceiver 302 and a radiotelephone 304 communicate through radio frequency (RF) signals 306. Transceiver 302 is a transceiver of a fixed site that serves a radio coverage area populated by radiotelephones, such as the radiotelephone 304. The radiotelephone 304 includes an antenna 308, a receiver 310, a transmitter 312, a synthesizer 314, a controller 316, and a user interface 318. The radiotelephone 304 operates through the power provided by a removable battery 320. The transceiver 302 transmits RF 306 signals to its radio coverage area populated by the radiotelephone 304. The antenna 308 transduces the RF signals 306 to the electric RF reception signals 309 and couples the reception signals of the RF. RF electrical 309 to receiver 310. Receiver 310 mixes electric RF reception signals 309 with a local oscillator frequency to generate intermediate frequency (IF) reception signals 311. Receiver 310 couples IF reception signals 311 to synthesizer 314. Synthesizer 314 provides additional mixing frequencies to convert IF 311 reception signals into reception signals of baseband (BB) 315. Synthesizer 314 adjusts and maintains reception signals of BB 315 at a desired amplitude for use by controller 316. Controller 316 processes reception signals of BB 315 into data reception signals 317. The data reception signals are coupled to the user interface 318 and issued to the user as an audible voice through a speaker (not shown) and as operational information through a visual display device (not shown). The voice inputted by the user through a microphone (not shown) from the user interface 318 is transduced and coupled to the controller 316 as data transmission signals 319. The controller 316 converts the data transmission signals 319 into signaling signals 319. BB transmission 321. The transmission signals of BB 321 are coupled to the synthesizer 314. The synthesizer converts the transmission signals of BB 321 into IF transmission signals 323. The transmission signals of IF 323 are coupled to the transmitter 312, the which mixes the transmission signals of IF 323 with a local oscillator frequency to convert the IF transmission signals 323 into electrical RF transmission signals 325. The electrical RF transmission signals 325 are further transduced by the antenna 308 and transmit to the transceiver 302 as RF signals 306. FIG. 4 is an illustration in block diagram form of the synthesizer 314 of the radio telephone or 304. The synthesizer 314 includes a down converter 401, a voltage controlled oscillator (VCO) 402, an operational amplifier 403, and an overconverter 404. The IF reception signals 311 generated by the receiver 310 of FIG. 3 are coupled to the sub-converter 401. Sub-converter 401 performs quadrature demodulation on the IF reception signals 311 by mixing IF reception signals 311 with in-phase and quadrature components of a BB 406 frequency signal input to sub-converter 401 a from the VCO 402. The resulting in-phase and quadrature reception signals are filtered by the down-converter 401 and coupled to the operational amplifier 403 as intermediate BB reception signals 408. The operational amplifier 403 adjusts the intermediate BB reception signals 408 at a desired amplitude and outputs the intermediate BB reception signals 408 to the controller 316 of FIG. 3 as reception signals of BB 315. The operational amplifier 403 includes an input stage 414, an intermediate stage 416, and an output stage 418. The transmission signals of BB 321 generated by the controller 316 of FIG. 3 are coupled to the converter 404. The over converter 404 mixes the transmit BB signals with the phase and quadrature components of an IF 420 frequency signal generated by the VCO 402. The mixed phase and quadrature IF signals are combined and emitted from the superconverter 404 as signals 323 transmitting signal. The transmit signals of IF 323 are further coupled to the transmitter 312 of FIG. 3. In the preferred embodiment, the components of the synthesizer 314 shown in Figure 4 are integrated and attached to a suitable substrate 430, such as a ceramic substrate. The substrate 430 is mounted in an IC package (not shown). The IC package provides connectors - 1 -
external devices for connecting the components of the synthesizer 314, such as the output stage 418 of the operational amplifier 403, to the external components, such as the controller 316 of FIG. 3, which may consist of one or more IC packets. When the BB reception signal 315 of an output of the IC packet of the synthesizer 314 is directly coupled to an input of the IC packet of the controller 316, the reception signal of BB 315 comprises a large amount of capacitance of the packet input of controller IC 316. In order to prevent synthesizer 314 from becoming unstable due to this high capacitance, it is necessary that output stage 418 provide a low impedance output. Figure 5 is a schematic illustration of the output stage 418 of the operational amplifier 403 of Figure 4. In the preferred embodiment, the output stage 418 is a unit gain and includes the buffer 100 of Figure 1 and the current amplifier 500. The buffer 100, which is a double-effect circuit, is energized by the supply voltage paths, first and second, 102, 104 of the battery 320 of FIG. 3. Although the second path of supply voltage 104 is shown as terrestrial, it will be recognized that output stage 418 could be energized through a sectional supply having voltage pathways - -
of positive and negative supply wherein the first supply voltage path 102 remains + VBB and the second supply voltage path 104 is designated, for example, -VBB. The buffer 100 is coupled between the input 106 and the output 116 of the output stage 418 and includes the intermediate storage devices, first and second, 108, 110 and the first and second bypass devices 112, 114 generally described with respect to Figure 1. More specifically, the first intermediate storage device 108 includes an npn transistor 501 having a base, a collector coupled to the first supply voltage path 102, and an emitter coupled to the output 116. The first intermediate storage device 108 is derived to a diode drop above the input voltage 105 by the first bypass device 112. The first bypass device 112 includes a pnp transistor 502 having a base coupled to the input 106 , a manifold coupled to the second supply voltage path 104, and an emitter coupled to the base of the npn transistor 501 of the first storage device in. Term 108, a first current source 503, and the first supply voltage path 102. In the preferred embodiment, the first current source 503 could be implemented by a PMOS transistor.
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The second intermediate storage device 110 includes a pnp transistor 504 having a base, a collector coupled to the second supply voltage path 104, and an emitter coupled to both the output 116 and the emitter of the npn transistor 501 of the first intermediate storage device 108. The second intermediate storage device 110 is derived to a diode drop below the input voltage 105 by the second bypass device 114. The second bypass device 114 includes an npn transistor 505 having a base coupled to the inlet 106, a manifold coupled to the first supply voltage path 102, and an emitter coupled to the base the pnp transistor 504 of the second buffer 110, a second current source 506, and the second supply voltage path 104. In the preferred embodiment, the second current source 506 could be implemented by an NMOS transistor. The buffer 100 operates in response to the input voltage 105 applied to the input 106 as previously described with respect to FIGS. 1 and 2. The intermediate storage devices, first and second, 108, 110 alternate their operation based on the magnitude of 1 input voltage 105 to provide the output signal capable of handling a load, such as controller 316 of FIG. 3. However, as established previously, the buffer 100, which performs the junction voltage limitations of the base emitter, is unable to fluctuate from track to track in an approximate manner and provide the output signal when the input voltage 105 is outside the range of intermediate voltage 210 of Figure 2 (when the input voltage 105 comes within about 0.8V of either the first supply voltage path 102 or the second supply voltage path 104. In order to increase the fluctuating capacity of pathway so that the output signal can be generated when the input voltage 105 is outside the intermediate voltage range 210 of FIG. 2, the current amplifier 500 is coupled to the memory oria intermedia 100. The current amplifier 500, which is energized by the supply voltage paths, first and second, 102, 104 and coupled between the input 106 and the output 116 of the output stage 418, assists the memory intermediate 100 to provide an output voltage 520 and the output current 117, collectively the output signal, at the output 116 when the input voltage 105 is outside the intermediate voltage range 210 of FIG. 2. The current amplifier 500 allows the output stage 418 to operate on about the - -
maximum voltage range 208 of FIG. 2 and still provide low impedance at output 116. Current amplifier 500, which is a path-to-path fluctuating circuit, includes a first amplifying device 508 and a second amplifying device 510. The first amplifying device 508 includes an NMOS transistor 507 having a gate coupled to the input 106, a source coupled to the second supply voltage path 104 and a drain coupled to the output 116. The first amplifying device 508 further includes a first current reflector 512. In the preferred embodiment, the first current reflector 512 comprises PMOS transistors 511 and 513. The first current reflector 512 is coupled between the drain of the NMOS transistor 507 of the first amplifier device 508 and the output 116. The second amplifier device 510 includes a PMOS transistor 509 having a gate coupled to the input 106, a source coupled to the first supply voltage path 102, and a drain coupled to the output 116. The second amplification device 510 further includes a second current reflector 514. In the preferred embodiment, the second current reflector 514 comprises NMOS transistors 517 and 518. The second current reflector 514 is coupled between the drain of the PMOS transistor 509 of the second amplifier device 510 and the output 116. The current amplifier 500 operates as follows. As the input voltage 105 approaches the first supply voltage path 102, the first amplifying device 508 is turned on and causes a first amplifying current 515 to flow in the drain of the NMOS transistor 507 of the first amplifying device 508. The first amplifier current 515 is reflected or reversed by the first current reflector 512 and coupled to the output 116. As the input voltage approaches the second supply voltage path 104, the second amplifier device 510 is turned on and causes a second amplifying current 516 to flow out of the drain of the PMOS transistor 509 of the second amplifying device 510. The second amplifying current 510 is reflected or reversed by the second current reflector 514 and coupled to the output 116. Figure 6 is an illustration in the form of a graph of a voltage transfer characteristic 600 of the output stage 418 of the fi 4 and 5. In response to the input voltage 105, the first and second intermediate storage devices 108, 110 and the first and second amplifying devices 508, 510 alternate their operation to provide the output voltage 520 and the output current 117. As the input voltage exceeds + VBB / 2 and approaches + VBB, as designated by the portion 602 of the transfer characteristic 600, the output voltage 520 is generally provided by the switching devices. intermediate storage, first and second, 108, 110 and the first amplifying device 508. Specifically, the first intermediate storage device 108 basically provides the output voltage 520 and the output current 117 for the values of the input voltage 105 between the point 601 on transfer characteristic 600 (or approximately + VBB / 2) and point 603 (or approximately + VBB-0.8V). Between point 603 and point 605 (or approximately + VBB-0.2V), the output voltage 520 is provided by the second buffer 110 and the output current 117 is provided by the first amplifier device 508. For the input voltages below + VBB / 2 and approaching 0V, as designated by the portion 604 of the transfer characteristic 600, the output voltage 520 and the output current 117 are generally provided by the storage devices intermediate, first and second, 108, 110 and the second amplifying device 510. Specifically, the second intermediate storage device 110 provides -
basically the output voltage 520 and the output current 117 for the values of the input voltage 105 between point 601 (or approximately + VBB / 2) and point 607 (or approximately 0.8V). Between point 607 and point 609 (or approximately 0.2V), the output voltage 520 is provided by the first intermediate storage device 108 and the output current 117 is provided by the second amplifying device 510. Because the devices bypass, first and second, 112, 114 ensure that the npn transistor 501 and the pnp transistor 504 of the intermediate storage devices, first and second, 108, 110, respectively, remain continuously on, the impedance at the output 116 remains low Although the known output stage of FIG. 1 comprises only the buffer 100, here, the output stage 418 exhibits ability to fluctuate from track to track and an increased range of operation; that is, the output stage 418 produces the output voltage 520 and the output current 117 when the input voltage 105 falls both within the intermediate voltage range 210 and outside the intermediate voltage range 210 but at least approximately 0.2V away of any of the first or second supply voltage pathways 102, 104. In the preferred embodiment, the first supply voltage path 102 is 3V and the second supply voltage path 104 is terrestrial or OV as shows, defining the maximum voltage range 208 as 3V. In comparison with the known buffer 100, which is limited to its operation in the intermediate voltage range 210 which includes only 1.4V of the 3V possible, the buffer 100 plus the current amplifier 500 are capable of providing the voltage of output 520 and output current 117 over a 610 amplified voltage range that includes 2.6V of the 3V possible. The amplified voltage range 610 is shown in FIG. 6 as it ranges from about 0.2V to about + VBB-0.2V. Figure 7 is a schematic illustration of an alternate output stage 700 for the operational amplifier 403 of Figure 4. The alternate output stage 700 is substantially identical to the output stage 418 illustrated in Figure 5, except that provides a switch to "turn on and turn off" the first and second amplifier devices 508, 510 in order to prevent unnecessary current drain when the first and second amplifier devices 508, 510 are not in use. The amplifying devices, first and second, 508, 510 do not need to provide the amplifying currents, first and - -
second, 515, 516 to assist the intermediate storage devices, first and second, 108, 110 at least until the input voltage 105 approaches the upper limit + VBB-0.8V or the lower limit 0.8V of the voltage range intermediate 210 (see figure 6). To carry out the current savings by not operating the first and second amplifying devices 508, 510 within the intermediate voltage range 210, an alternating current amplifier 701 includes a first switch 702 and a second switch 704 coupled to the devices amplifiers, first and second, 508, 510, respectively. The first switch 702 includes a first switching device 706. The first switching device 706 includes an NMOS transistor 707 coupled to the first amplifying device 508 in a differential pair configuration. The NMOS transistor 707 of the first switching device 706 includes a gate, a drain coupled to the first supply voltage path 102, and a source coupled to the NMOS transistor source 507 of the first amplifying device 508. The first device switch 706 includes a third current source 708 coupled to the sources of the NMOS 507 transistors, 707 of the first amplifier device 508 and the first switching device 706, respectively, to derive the differential pair configuration. The third current source 708 could be implemented by an NMOS transistor. The first switch 702 includes a first switch bypass device 710 coupled to the first switch device 706. The first switch bypass device 710 includes an npn transistor 711 having a base, a manifold coupled to the first supply voltage path 102. , and an issuer. The base is coupled to the collector to carry out a diode drop through an npn transistor 711. The first switch bypass device 710 includes a first resistor 712 coupled between the emitter of the npn transistor 711 and the gate of the transistor of NMOS 707 of the first switching device 706. The first resistor 712 is evaluated to provide approximately one-half of a diode drop therethrough. The first switch bypass device 710 includes a fourth current source 714 coupled below the first resistor 712 and between the gate of the NMOS transistor 707 of the first switching device 706 and the second supply voltage path 104. The fourth source of current 714, which could be made by an NMOS transistor, derives the first bypass device 710 to the operation.
The first switch 702 prevents the first amplifier device 508 from generating the first amplifier current 515 until the input voltage 105 approaches the upper limit + VBB-0.8V of the intermediate voltage range 210. The first resistor 712 and the npn transistor 711 of the first switch bypass device 710 set the gate voltage of the NMOS transistor 707 of the first switching device 706 to approximately one and a half diode drops below the first supply voltage path 102. The differential pair configuration prevents the first amplifying device 508 from turning on and supplying the first amplifying current 515 until the input voltage 105 in the gate of the NMOS transistor 507 of the first amplifying device 508 meets or exceeds approximately one and a half diode drops below the first supply voltage path 102. In the preferred embodiment of the alternate output stage 700 of Figure 7, the first amplifier device 508 is turned on and supplies the first amplifier current 515 when the input voltage 105 in the gate of the NMOS transistor 507 of the first amplifier device 508 exceeds approximately + VBB-1.2V. As the input voltage in the gate of the NMOS transistor 507 of the first amplifying device 508 falls below - -
of about + VBB-1.2V the first amplifier device 508 goes off again. The second switch 704 includes a second switching device 716. The second switching device 716 includes a PMOS transistor 717 coupled to the second amplifying device 510 in a differential pair configuration. The PMOS transistor 717 of the second switching device 716 includes a gate, a drain coupled to the second supply voltage path 104, and a source coupled to the source of the PMOS transistor 509 of the second amplifying device 510. switching 716 includes a fifth current source 718 coupled to the sources of the PMOS transistors 509, 717 of the second amplifying device 510 and the second switching device 716, respectively, to derive the differential pair configuration. The fifth current source 718 could be implemented by a PMOS transistor. The second switch 704 includes a second switch bypass device 720 coupled to the second switch device 716. The second switch bypass device 720 includes a PNP transistor 721 having a base, a collector, and an emitter coupled to the gate of the transistor of PMOS 717 of the second switching device 716. The base is coupled to the collector to carry out a diode drop across the PNP transistor 721. The second switch bypass device 720 includes a second resistor 722 coupled between the collector of the transistor of pnp 721 and the second supply voltage path 104. The second resistor 722 is evaluated to provide about one-half of a diode drop therethrough. The second switch bypass device 720 includes a sixth current source 724 coupled between the first supply voltage path 102 and the gate of the PMOS transistor 717 of the second switching device 716. The sixth current source 724, which could be by means of a PMOS transistor, the second bypass device 720 drifts towards the operation. The second switch 704 prevents the second amplifier device 510 from generating the second amplifier current 516 until the input voltage 105 approaches the lower limit + 0.8V of the intermediate voltage range 210. The second resistor 722 and the PNP transistor 721 second bypass switch device 720 set the gate voltage of the PMOS transistor 717 of the second device switching 716 to about one and a half diode drops above the second supply voltage path 104. The differential pair setting of the second switch 704 prevents the second amplifying device 510 from turning on and supplying the second amplifying current 516 until the input voltage 105 in the gate of the PMOS transistor 509 of the second amplifying device 510 is met or goes below approximately one and a half diode drops above the second supply voltage path 104. In the preferred embodiment of the step alternate output 700 of figure 7, the second amplifying device 510 is turned on and supplies the second amplifying current 516 when the input voltage 105 in the gate of the PMOS transistor of the second amplifying device 508 drops below approximately + 1.2V. As the gate input voltage of the PMOS transistor 509 of the second amplifier device 510 exceeds about 1.2V, the second amplifier device 510 is turned off again. Figure 8 is an illustration in flowchart form of a method for amplifying the input voltage 105 to the output voltage 520 and the output current 117 (collectively, the output signal) to drive a load coupled to a stage output of an operational amplifier, such as an output stage 418 or 700. Initially, in step 800, the input voltage 105 is received at the input 106 of the output stage 418, 700 illustrated in FIGS. 5 and 7. If the input voltage 105 is within the intermediate voltage range 210 (see figure 6) of 0.8V to + VBB-0.8V, as determined in decision step 802, the output signal is generated basically by the intermediate, first and second buffer devices 108, 110 of buffer 100 in step 804 and then output to output 116 in step 808. The npn transistor 501 of the first buffer 108 outputs current to the exit 116 when the input voltage 105 is between approximately + VBB / 2 and approximately + VBB-0.8V. The pnp transistor 504 of the second buffer 110 descends current to the output 116 when the input voltage 105 is between about + VBB / 2 and about 0.8V. If the input voltage 105 is not within the intermediate voltage range 210 of 0.8V to + VBB-0.8V, as determined in decision step 802, the output signal is basically generated by the amplifying devices, first and second. second, 508, 510 of the current amplifier 500 in step 806 and then output to the output 116 in step 808. The NMOS transistor 507 provides the first amplifier current 515 when the input voltage 105 is between approximately + VBB -0.8V and approximately + VBB-0.2V. The PMOS transistor 509 provides the second amplifying current 516 when the input voltage 105 is between about 0.2V and about 0.8V. Although illustrated as a bicmos implementation, it will be recognized that the current amplifier 500 and the first and second switching devices 702, 704 could be implemented in any complementary linear IC technology, such as CMOS or bipolar. Also, although shown implemented with bipolar devices, the buffer 100 could be implemented using any complementary technology such as conventional CMOS. In summary, an output stage for an operational amplifier energized by supply voltage paths, first and second, and including a buffer portion and an amplifier portion, provides a low output impedance and is capable at the same time to fluctuate from track to track roughly. The buffer portion includes first and second buffer storage transistors each having a base coupled to an input of the output stage and an emitter coupled to an output of the output stage to provide a low impedance output. . The intermediate storage transistors, first and second, are derived to operation by first and second bypass devices, respectively. Because the electrical characteristics of the buffer storage transistors, first and second, the buffer portion is limited to producing a load that handles the output signal when the input voltage is at least one diode drop away from any of supply voltage pathways, first or second. By coupling the amplifier portion between the input and the output, the output stage is capable of supplying the load that handles the output signal for the input voltages within a diode drop of any of the supply voltage paths, first or second. The amplifier portion includes a first transistor amplifier that supplies a first amplifier current to the output in order to provide the load that drives the output signal when the input voltage is within a diode drop of the first voltage path of the amplifier. supply. A second transistor amplifier of the amplifier portion supplies a second amplifier current to the output to provide the load that drives the output signal when the input voltage is within a diode drop of the second supply voltage path. The first and second branch transistors ensure that the first and second buffer storage transistors remain on while the first and second amplifier transistors provide the first and second amplifier currents, thus ensuring a low impedance output.