MXPA05012015A - Linear time code receiver - Google Patents

Abstract

An Linear Time Code (LTC) receiver (10) for receiving and decoding a LTC frame of the type used in connection with film and television and accompanying audio includes a first counter (12) that measures the number of reference clock periods within the duration of a bi-phase mark signal interval to yield a timing reference for extracting the payload from the LTC frame. A second counter (16) detects a sync field within the LTC frame to establish the LTC frame direction. A third counter (18) serves to count the number of symbols in the LTC frame. A state machine (12) responsive to the counts of the first, second and third counters (14, 16,18), serves to (a) detect a valid synchronization sequence within an incoming LTC frame;(b) determine the LTC frame direction, (c) decode (extract) payload information from the LTC frame;and (d) transfer the payload information in an order determined by the LTC frame direction.

Description

LINEAR TIME CODE RECEIVER CROSS REFERENCE WITH RELATED REQUESTS This application claims priority in accordance with 35 U.S.C. 119 (e) of U.S. Patent Application Serial No. 60 / 469,437, filed May 9, 2003, the teachings of which are incorporated herein by reference.

FIELD OF THE INVENTION This invention relates to a technique for decoding (extract) a linear time code (LTC) frame of the type used with film and television and audio annex.

BACKGROUND OF THE INVENTION As described in Standard 12M of Society for Motion Picture and Television Engineers (SMPTE): "Time Code and Control for Television, Audio and Film" ("Time code and control for television, audio and movies"), a linear time code frame (LTC) serves as a mechanism to communicate a digital time stamp and control code information to be used in television, films and attached audio systems operating at 30, 29, 97, 25 and 24 frames / second. Each LTC code frame contains 80 numbered bits from 0 to 79 that are generated serially starting with bit 0 for a "forward" time code and bit 79 for an "inverse" time code. Each successive LTC frame starts where the previous frame ended. Each 80-bit LTC frame comprises a 64-bit LTC data word (payload) and a 16-bit static synchronization sequence. Each LTC frame contains a unique time frame for an associated video or movie frame that includes four binary-encoded-decimal (BCD) fields that represent hours, minutes, seconds, and frames. The nominal bit rate for an LTC frame is Fs = 80 * Fr, where Fr is the nominal frame speed of the video or associated movie. In addition to the time stamp formatted in BCD, the 32 bits are available within a LTC data word for user-defined purposes. Figure 1 illustrates an exemplary LTC framework. The sixteen bits in the synchronization sequence within the LTC frame allow the LTC receiver equipment to delineate the LTC frames exactly and identify the bit positions within each frame. The LTC frame synchronization pattern is unique in that the same bit combination can not be generated by any combination of valid data values in the rest of the frame. The twelve central bits of the 16-bit synchronization pattern are a logical one. The two front bits are both zero, while the two back bits are logical zero followed by a logical one. The different patterns of front and back bit pairs allow a LTC receiver to determine the direction (forward / reverse) of the LTC frame. The 80-bit NRZ binary data comprising an LTC frame is a biphase frame encoded in accordance with the following standards specified in Standard 12M: A transition occurs at each bit symbol boundary regardless of the bit value. A logical one is represented by an additional transition occurring at a midpoint of the bit symbol; and A logical zero is represented by not having additional transitions within the bit symbol. A coded bi-phase signal has no component, is insensitive to amplitude and polarity and contains a significant spectral energy at bit rate. Therefore, an LTC frame qualifies as a self-synchronized data stream because the phase locked circuit (PLL) can be blocked to this current and extract the bit rate clock. The LTC frame can be recorded on a linear audio tape track. Until now, LTC receivers have used an analog PLL. As described above, the LTC framework uses a synchronization technique that makes use of a transition at the boundary of the bit symbol for binary symbol values of logical zero and logical one, plus an additional symbol half transition for the symbols of bits of a logical one. Because the frame has a high spectral energy at symbol speed, the PLL can block the frequency in its local oscillator at the symbol speed of the LTC frame coded for bi-phase marking. A "data slicer" circuit that operates at a multiple of recovered symbol clock can more than recover the 64 payload bits per frame of time coded data. Current LTC receivers using an analog PLL experience the disadvantage that the PLL clock recovery circuit has to operate at a symbol rate of x / 30 to 80x at the nominal symbol rate of 2400 bits / sec for a format of video of 525 lines / 60 fields (80 bits / frame x 30 frames / sec). When designing a voltage controlled oscillator (VCO) that operates over this wide input reference range, it often presents some difficulty. In addition, analog current typically requires calibration to achieve repeatable results.

BRIEF DESCRIPTION OF THE INVENTION Briefly, in accordance with the present principles, a method for receiving a linear time code (LTC) framework is provided. The method begins after detecting a valid sequence of synchronization within an incoming LTC frame while measuring a predetermined symbol interval relative to a reference clock. Then the LTC frame address is determined. With the use of the measured symbol interval, the payload information is extracted from the LTC framework and that payload information is transferred for storage in a fixed order.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a graphic representation of a conventional LTC framework. Figure 2 illustrates a block schematic diagram of a linear time code receiver (LTC) in accordance with a preferred embodiment of the present principles. Figure 3 illustrates a state diagram of a state machine within the LTC receiver of Figure 2 to illustrate machine states for effecting synchronization detection and symbol interval measurement. Figure 4 illustrates a state diagram for the state machine within the LTC receiver of Figure 2, to illustrate machine states for effecting bitstream direction detection; and Figure 5 illustrates a state diagram for a state machine inside the LTC receiver of Figure 2, to illustrate the machine states for effecting extraction of the LTC frame payload.

DETAILED DESCRIPTION OF THE INVENTION Figure 2 illustrates a block schematic diagram of a LTC receiver 10 in accordance with a preferred embodiment of the present invention for decoding (extracting) payload information from an LTC frame of the type illustrated in Figure 1 The receiver 10 of Figure 2 includes a state machine 12 having fifty-five states. The states of the state machine 12, described herein with respect to the state diagrams of Figures 3-5, perform the payload decoding (extraction) of the LTC frame by the steps of: 1. Detecting a valid synchronization sequence of bi-phase marking while simultaneously measuring the half-symbol interval of the current frame. 2. Detect the bi-phase marking current direction: forward or reverse; and 3. Extract the 64 bits of data from the coded bi-phase stream for storage in the correct order of bits, regardless of the current direction. To facilitate the extraction of the payload from the LTC frame, the LTC receiver 10 includes three counters 14, 16, 18, all synchronized by a 27 MHz clock 20 which also synchronizes the state machine 12. The counter 14 carries the designation of "Half-symbol duration counter", since the counter counts the number of clock periods of the reference clock of 27 MHz that occur within the duration of the bi-phase mark half symbol interval. The half-symbol duration counter 14 starts counting after receiving a signal "Intervalbetterbrakedoor" from the state machine 12 and the counter restarts in response to a reset signal "delay interval enable start pulse" from the state machine.

To better understand how the count of the half symbol duration counter 14, which provides a measurement of the half symbol interval, should refer to the format of the LTC frame illustrated in Figure 1. As shown, the bits of the 16 bit synchronization word are encoded with bi-phase mark. By virtue of such bi-phase mark coding, bits one undergo a change in phase at twice the symbol rate. Thus, by counting the number of 27 MHz clock periods between the alternates of the one bits in the synchronization word, the half symbol duration counter 14 provides an account corresponding to half the symbol rate to facilitate the decoding (extraction) of the data contained in the 64-bit payload of the LTC frame of Figure 1. The half-symbol duration counter 14 of Figure 2 supplies its account to the state machine 12 and to a register 22. The record 22, designated as "interval account reference register" stores the account of the counter 14 for entering it into the state machine 12 after receipt of a signal from the state machine "useful count beforehand". In this way, the interval account reference register 22 provides the account to the state machine 12 during the synchronization detection state of the decoding (extraction) process. The previous interval count serves as a time reference to analyze the 64-bit payload of the LTC frame of Figure 1. The number of 27 MHz clock periods that occurs within a bi-phase half-symbol mark for a Specific range of frame speeds appears in Table 1 below, where X is a nominal frame speed LTC.

TABLE 1 The minimum required account for clock periods is seventy, while the maximum account is 210,947. The half-symbol duration counter 13 has a width of eighteen bits (218 = 266, 144) to accommodate the current speeds X / 30 LTC. The 27 MHz reference clock 20 provides sufficient resolution for the very short bit symbol periods encountered during current speeds of 80 * X. The counter 16 carries the designation "synchronization counter" since the counter counts the number of decoded bits of the 16-bit synchronization field of the LTC frame of Figure 1. The synchronization counter 16 starts counting in response to reception from "synchronizationincrementincrease" of the state machine 12 and it is restarted after receiving a pulse designated as "synchronization with backstop pulse". The synchronization counter 16, which has a width of five bits, serves to detect the twenty-four ones and alternating logical zeros of a duration of half a symbol in the synchronization field of the LTC frame. This sequence constitutes the bi-phase frame-coded equivalence of twelve consecutive logical ones comprising the synchronization field within the binary data frame NRZ (non-return to zero) of 80 bits comprising the LTC frame. The counter 18 carries the designation "data symbol counter" as it serves to count the number of decoded (extracted) data words shifted out of the state machine 12 within the sixty-four bit shift register 24. The data symbol counter 18 begins to count in response to a "high-count" signal received from the state machine 12. The address at which the shift register 24 shifts the data words to an intermediate memory 26 of sixty-four bits depends on the state of a "current direction" signal received by the shift register 24 from the state machine 12. The intermediate bit memory 26 serves to emit the bits received from the shift register 24 in response to the state of a "Valid MarkerCargalmpulse" signal received from the state machine 12. As its name implies, the ValidMarcoCargalmpulso signal is used to activate the shift register 26 after a determination by the state machine 12 that the valid frame information has been sent to the shift register 24. In addition to the different signals described here, the state machine also generates other signals. These signals include: (a) an "LTC current address label" which designates the direction of the LTC frame; (b) a "Valid Synchronization Tag", which designates whether the synchronization of the LTC frame is valid; and (c) an "OK transfer signal" which reflects whether a valid transfer of the LTC data has occurred. "The proper operation of the state machine 12 depends on its ability to change the states in synchrony with the bi-mark transitions. -phase within an incoming LTC frame Therefore, the filtering of an incoming LTC frame becomes important For this purpose, the LTC receiver of Figure 2 includes a micro-cut filter 30 at its input to filter the transitions of bi-phase marking of a duration less than the minimum duration of half a symbol associated with the current velocity X / 30. Assuming a reference clock frequency of 27 MHz, the minimum duration of half a symbol is seventy, Figure 3 illustrates graphically the first sixteen states of the state machine 12 associated with synchronization detection and symbol interval measurement As described in more detail below, sixteen transitions are required. Statements to detect the synchronization pattern and measure the duration of half-mark symbol bi-phase of the twenty-four synchronization patterns 0-1. To detect the synchronization sequence, the interval count, in the 27 MHz clock periods of the period between the bi-phase mark transitions through the half-symbol interval counter is captured continuously. When the current interval count is within +/- 25% of the previous interval count, the synchronization counter 16 is incremented, otherwise the synchronization counter is reset to zero. When the count of the synchronization counter 16 reaches twenty-four, the "valid synchronization" label is set and the state machine 12 changes to a bit current direction detection sequence of Figure 4. The previous interval count stored in the interval account reference register 22 now becomes the reference for the duration of half a bi-phase mark symbol (half of a logical NRZ 1) for the remainder of the frame. An interval count within +/- 25% of the double of this count indicates the duration of the complete bi-phase mark symbol (a logical NRZ 0). The synchronization detection and the symbol interval detection process after the execution of a 0 state (the restart state, which occurs at the initial power-up), after entering the 0 state, the counters 12, 14 and 16 become to restart, such as the sync tag and the LTC stream address tag. The state machine 12 of Figure 2 remains in the 0 state as long as the bi-phase mark symbol value is kept at zero. After a change of the bi-phase mark symbol value to a logic 1 level, the state machine 12 enters the state 1 of Figure 3 and activates the half symbol duration counter 14 of Figure 2 to start to count. The half-symbol duration counter 14 continues until the bi-phase mark symbol value returns to zero where the state machine 12 enters state 2, whereby the half-symbol duration counter 14 stops the account , and your current account is stored. After state 2, state 3 is activated, whereby the mean symbol duration counter 14 is restarted. The state 4 is activated after the state 3 and the counter 14 of the half-symbol duration starts again counting. The state machine 12 remains in state 4 as long as the bi-phase mark symbol value is kept at zero. When the bi-phase mark symbol value is changed to a logical one, the state machine 12 enters the state 5 of Figure 3, whereby the half-symbol duration counter 14 stops the count. After state 5, the state machine 12 enters one of several states depending on the value of the current interval count (CIC) of the half symbol duration counter 14 and its relation to the previous interval count (PIC) of the register 22 interval account reference. When the CIC exceeds a maximum account (max_account), it represents a condition where the actual LTC symbol speed exceeds the maximum allowable LTC bit symbol speed, or the CIC is less than a minimum account (min_account), which represents a condition where the actual bit symbol speed LTC is below the minimum permissible symbol speed LTC, then the state machine 12 returns to the state 0 after the state 5. In this way, the state machine 12 Restarts the synchronization detection and the symbol interval measurement process after finding a symbol rate that is too low or too high. After finding the min-account condition <; CIC < max_account, true, then the state machine makes a determination of whether the .75 PIC < CIC < 1.25 PIC is true. In other words, the state machine 12 makes a determination after! state 5 to see if CIC is within 25% of the PIC value. When this is the case, the state machine 12 enters state 6, whereby the state machine 12 increments the synchronization counter 16 and then stores the current count of the half symbol duration counter 14. After state 6, state machine 12 enters state 7 of Figure 3, whereby a check is made as to whether the count (i.e., sync account) of sync counter 16 of Figure 2 is equalized or exceeds twenty-three. After finding that this condition was achieved, the state machine 12 knows whether there is proper synchronization with the received LTC frame, which enables the state machine to transition the bitstream direction detection sequence upon entering the state. 17 of Figure 4, described below. In the event that the machine 12 finds the synchronization count of the synchronization counter 16 less than twenty-three during the state 7, which indicates a failure to detect a complete synchronization pattern, the state 8 is activated, whereby the counter 14 of half symbol duration begins to count. State 8 remains active whenever the bi-phase mark symbol value remains in a logical one. Once the bi-phase mark symbol value is changed to a logical zero level, the state machine 12 of Figure 2 enters state 11 of Figure 3, whereby the medium duration counter 14 symbol stops the account. From state 11, state machine 12 enters state 12 of FIG. 3 after finding condition 75 PIC < CIC < 1.25 true PIC. During state 12 of Figure 3, the state machine 12 of Figure 2 increments the synchronization counter 16 and stores the current count of the half symbol duration counter 14 before entering state 13. During state 13, the state machine 12 resets the half symbol duration counter 14 and also determines whether or not the synchronization exchange equals the synchronization counter 16 or exceeds twenty three. When this is the case, the state machine 12 proceeds to the bitstream direction detection sequence upon entering the state 27 of FIG. 4, which will be described later. When so, during state 11 of Figure 3, condition .75 < PIC < CIC < 1.25 PIC is not true, the current value of the interval account reference register 22 is an invalid half symbol duration account and the search for a valid synchronization pattern must be restarted. The state machine 12 enters the state 15 during which the state machine resets the synchronization counter 16 and stores the interval count of the half symbol duration counter 14. This account is the new time reference to detect a valid synchronization pattern. The state 16 is then activated, during this, the state machine 12 resets the half-symbol duration counter 14, of Figure 2. After the 16 state, or after the 13 state, when the synchronization account is not successful or exceeds 23, the state 14 is activated during which the half-symbol duration counter 14 starts counting. The state 14 remains active until the bi-phase mark symbol value becomes 1. As described above, the state machine 12 enters the state 6 after state 5, where it finds both conditions min_account < CIC < max < account and .75 PIC < CIC < 1.25 PICs are true. However, in case the state machine 12 finds the conditions min_account < CIC < max < true account, but condition .75 PIC < CIC < 1.25 false PIC, then state 9 is activated. This state transition indicates that the actual value in the interval account reference register 22 is an invalid half-symbol account and the search for a valid synchronization pattern must be restarted, whereby the synchronization counter 16 is restarted and the interval count of the half symbol duration counter 14 is stored. This value is the new time reference to detect a valid synchronization pattern. After this, the state 10 is activated, whereby the half-symbol duration counter 14 is restarted before entering the state 8 described above. Figure 4 illustrates the state diagram showing the states associated with frame bit stream detection LTC. There are two separate sequences of 10 states for the determination of current direction. The sequence of 10 states that is selected depends on the polarity of the synchronization field detected during the synchronization detection status sequence described above with respect to Figure 3. The current direction detection sequence searches for the coded equivalence of the bi-mark. -phase of the bit fields NRZ "01" front or "00" inverse. When the address is determined, the address label is set in forward or inverse, and the state machine is changed to the decoding (extracting) data sequence, described herein with respect to Figure 5. With reference to the Figure 4, the first of two states of ten sequences with the address detection of bitstream starts with the state 17 which is activated after the state 7 of Figure 3, whereby, the counter 14 of half-time symbol of the Figure 2 starts counting, and the sync tag is adjusted. When activated, this tag indicates that a valid LTC synchronization pattern has been detected. State 17 remains active as long as the bi-phase mark symbol value is maintained at a logical one level. After the transition of the bi-phase mark symbol value to a logical zero level, the state 18 is activated and the half symbol duration counter 14 stops the count. Then, state 19 is activated when condition 1.75 PIC <; CIC < 2.25 PIC is true. When the condition is false, the detected address bit pattern is invalid, and the state machine 12 is reset upon changing to state 0. When the state 19 is activated, the state machine 12 of FIG. 2 resets the counter 14 of duration of half symbol. The state 20 is activated after the state 19, and the half-symbol duration counter 14 starts the count. State 20 remains active as long as the value of the bi-phase mark symbol remains at logical zero. Once the bi-phase mark symbol value is changed to a logical one level, the state machine 12 enters state 21. During state 21, the half symbol duration counter 14 stops the count. After the state lf 21, the state machine 12 of Figure 2 enters state 22 when condition 1.75 PIC < CIC < 2.25 PIC is true, or enters state 23 when condition .75 PIC < CIC < 1.25 PIC is true. When none of the conditions is true, the detected address bit pattern is invalid and the state machine 12 resets upon changing to state 0. The state entry 22 reflects the detection of a reverse address synchronization pattern. During state 22, state machine 12 resets the half symbol duration counter 14 and sets the address label to "REVERSE" to indicate detection of a reverse synchronization pattern before advancing to state 37 described with reference to the Figure 5. As described, state 23 is activated after state 21 when condition 75 PIC < CIC < .25 PIC is true. During state 23, the half-symbol duration counter 14 is reset and the address label is set to FRONT. After this, the state 24 is activated and the counter 14 of half symbol duration begins the count. State 24 remains active as long as the bi-phase mark symbol value is maintained at a logical one level. Once the bi-phase mark symbol value changes to a logical zero, the state 25 is activated and the half symbol duration counter 14 stops the count. After state 25, state 26 is activated when .75 PIC < CIC < 1.25 PIC is true, otherwise state 0 is activated. The transition to state 0 indicates that an invalid address bit pattern was detected and the state machine 12 is reset. After the state 25 is activated, the half symbol duration counter 14 stops the count. Then, the state 26 is activated during which the half-symbol duration counter 14 is reset. As described in more detail with respect to Figure 5, state 44 is activated after state 26. With reference to Figure 4, state machine 12 enters state 17 after state 13 of Figure 3, then of determining that the synchronization account of the synchronization counter 16 equals or exceeds twenty-three. After entering the state 27, the state machine 12 of Figure 2 starts the half symbol duration counter 14 and adjusts the synchronization tag to mention a valid synchronization condition. State 27 remains active as long as the bi-phase mark symbol value is maintained at a logical zero level. Once the bi-phase mark symbol value changes to a logical 1 level, the state 28 is activated and the half symbol duration counter 14 stops the count. State 29 is activated after state 28 when condition 1.75 PIC < CIC < 2.25 PIC is true. Otherwise, the 0 state is activated. The change to a 0 state indicates that an invalid address bit pattern was detected, and the state machine 12 is restarted. When the state 29 is activated, the state machine 12 of Figure 2 resets the half symbol duration counter 14. The state 30 is activated after the state 29, whereby the counter 14 of half symbol duration begins the count. State 30 remains active as long as the bi-phase mark symbol value is maintained at a logical one level. Once the bi-phase mark symbol value changes to a logical zero level, the state 31 is activated, whereby the half-symbol duration counter 14 stops the count. From state 31, state machine 12 of Figure 2 enters state 32 when condition 1.75 PIC < CIC < 2.25 PIC is true, or enters state 33 when condition .75 PIC < CIC < 1.25 PIC is true. When none of the conditions is true, the state machine 12 enters state 0. The change to state 0 indicates that an invalid address bit pattern was detected and the state machine 12 is reset. After entering state 32, the half-symbol duration counter 14 is reset, and the address label is set to "INVERSE". Then, the state machine 12 enters the state 44 of Figure 5 as described below. After finding condition 75 PIC <; CIC < 1.25 true PIC, the state machine 12 of Figure 2 enters the state 33 of Figure 4. During state 33, the state machine 12 resets the half symbol duration counter 14 and sets the address label to " FORWARD". Then, the state machine enters the state 34, whereby the counter 14 of half symbol duration starts the count. The state 34 remains active as long as the bi-phase mark symbol value is maintained at a logical zero value. Once the biphase mark symbol value changes to a value of a logical one, the state machine 12 enters state 35, whereby the half-symbol duration counter 14 stops the count. During state 35, the half symbol duration counter 14 stops the count. When condition 75 PIC < CIC < 1.25 PIC is true, then state 36 is activated after state 36 is activated, whereby the half symbol duration counter 14 is reset before advancing to state 37 of Figure 5. Otherwise, when the Condition 75 PIC < CIC < 1.25 PIC is not true, state 0 is activated after state 35. The transition to state 0 indicates that an invalid address bit pattern was detected and the state machine 12 is reset. Figure 5 illustrates the nineteen states of the state machine 12 associated with the 64-bit decoding in the payload of the LTC frame of Figure 1. The 19-state data decoding sequence uses a half-time symbol count. bi-phase mark stored in the interval account reference register 22 as the time reference for decoding the 64-bit data payload in the LTC frame of Figure 1. As will be better understood from the description of the individual states of the decoding sequence, two consecutive transitions with durations within +/- 25% of the mean reference symbol count are decoded as an NRZ logical 1, while a transition with a duration within +/- 25% of the double of the reference account is decoded as an NRZ logical 0. Each sequential decoder loads the equivalent NRZ bit into the shift register 24 of FIG. 2 at the address indicated by the address tag, and increments the data symbol counter 18 When the data symbol counter count reaches sixty four. , the content of the shift register 24 is transferred to the 64-bit buffer register 26, and the OK tag is set. This record is read while the next frame undergoes decoding. With reference to Figure 5, the duration sequence for a true-forward or true-inverse bi-phase marking current begins after the entry of state 37 after any of states 22 or 36 of Figure 4. As shown in FIG. described herein, the duration sequence begins for a complementary-forward or complementary-reverse bi-phase marking current after entry to state 44 of Figure 5, after one of states 26 or 32 of Figure 4. Then Upon entering the state 37, the state machine 12 causes the half symbol duration counter 14 to start counting. State 37 remains active as long as the value of the bi-phase mark symbol is maintained at a logical one level. After a transition from the bi-phase mark symbol value to a logical zero, the state 38 is activated, whereby the half-symbol duration counter 14 stops the count. Starting from state 38, state machine 12 of Figure 2 enters state 51 when condition 1.75 PIC < CIC < 2.25 PIC is true, or enters state 33 when condition .75 PIC < CIC < 1.25 PIC is true. When none of the conditions is true, the state machine 12 enters state 0 of Figure 3. By changing to the 0 state it indicates that an invalid payload bit pattern was detected, and the state machine 12 is reset. After entering state 39 of Figure 5, the state machine 12 restarts the half symbol duration counter 14. Then, the state 40 is activated, whereby the counter symbol duration 14 starts the count. State 40 remains active as long as the bi-phase mark symbol value is kept at a logical zero. After the transition of the bi-phase mark symbol value to a value of a logical one, the state 41 is activated and the half symbol duration counter 14 stops the count. After state 41, state 42 is activated when condition .75 PIC <; CIC < 1.25 PIC is true, otherwise, state 0 of Figure 3 is activated. By changing to state 0 it indicates that an invalid data payload bit pattern was detected, and the state machine 12 is reset. After entering the state 42 of Figure 5, the state machine 12 of Figure 2 resets the half symbol duration counter 14 and increments the data symbol counter 18 of Figure 2. Also, during the 42 state, the state machine 12 adjusts a LTC_data variable to a value of a logical one. This value is shifted simultaneously within the 64-bit offset record in one direction (first MSB or first LSB) dictated by the value of the address label ("FRONT" or "INVERSE"). The LTC_data is the NRZ equivalent of the decoded bi-phase payload bit.

After state 52, state 43 is activated, whereby a comparison occurs between the account of the data symbol counter 18, hereinafter called account_symbol, and the value sixty-four. When the account_equal equals sixty-four, it is indicated that all the bits of the 64-bit payload of the LTC framework have experienced the duration, then the frame duration has been successful, and state 55 is activated, whereby, the content of the 64-bit shift register 24 is transferred to the 64-bit buffer register 26 before advancing to the 0 state. After changing to the 0 state, the state machine 12 is ready to begin decoding a subsequent LTC frame . Otherwise, when the account_symbol does not exceed sixty-four, then after the state 43, the state 37 is activated again to begin the process of decoding a successive symbol value. After state 38, state 51 is activated when condition 1.75 PIC < CIC < 2.25 PIC is true, better than entering state 39 when .75 PIC < CIC < 1.25 PIC is true. After entering state 51, the state machine 12 resets the half symbol duration counter 14 and increments the data symbol counter 18. Also, the state machine 12 adjusts the LTC_data variable to a value of logical zero. This value is shifted simultaneously within the 64-bit offset register in one direction (first MSB or first LSB) dictated by the value of the address label ("FRONT" or "INVERSE"). The state 52 is activated after the state 51 and a verification of the value of the account_token of the symbol counter 18 of Figure 2 occurs at this time. When the account_square equals or exceeds sixty-four, state 55 is activated. Otherwise, when the account_symbol is less than sixty-four, state 44 is activated. State 44 of Figure 5 is activated after the states 26 and 32 of Figure 4. After entering state 44, the status machine 12 causes the half symbol duration counter 14 to start the count. State 44 remains active as long as the bi-phase mark symbol value is maintained at a logical zero level. After a transition from the bi-phase mark symbol value to a logical one, the state 45 is activated, whereby the half-symbol duration counter 14 stops the count. From state 45, state machine 12 of Figure 2 enters state 53 when condition 1.75 PIC < ClC < 2.25 PIC is true, or enters state 46 when condition .75 PIC < CIC < 1.25 PIC is true. When none of the conditions is true, the state machine 12 enters a state 0 of Figure 3. By changing to a state 0 it indicates that an invalid data payload bit pattern was detected, and the state machine 12 it reboots. After entering state 46, the state machine 12 resets the half symbol duration counter 14. Then, the state 47 is activated, whereby the state machine 12 causes the half symbol duration counter 14 to start the count. State 47 remains active as long as the bi-phase mark symbol value is maintained at a logical one level.

After the transition of the bi-phase mark symbol value to a logical zero value, the state 48 is activated, and the half symbol duration counter 14 stops the count. After state 48, state 49 is activated when condition .75 PIC < CIC < 1.25 PIC is true, otherwise, state 0 is activated. When changing to a state 0 it is indicated that an invalid data payload bit pattern was detected and the state machine 12 is reset. After entering state 49 of Figure 5, the state machine 12 of Figure 2 resets the half symbol duration counter 14 and increments the data symbol counter 18 of Figure 2. Also, at this time, the state machine 12 adjusts a variable LTC_data to a value of a logical one. This value is shifted simultaneously within the 64-bit offset register in one direction (first MSB or first LSB) dictated by the value of the address label ("FRONT" or "INVERSE"). After state 49, state 50 is activated, so a comparison between the account_symbol and the value sixty-four occurs. When the account_equal equals or exceeds sixty-four, it is indicated that the LTC frame duration has been successful, and the state 55 is activated, whereby, the content of the 64-bit shift register 24 is transferred to the record 26 of 64-bit buffer before advancing to state 0 of FIG. 2. After changing to state 0, the state machine 12 is ready to begin decoding a subsequent LTC frame. Otherwise, when the account_symbol does not exceed sixty-four, then after the state 50, the state 44 is activated again to begin the process of decoding a successive symbol value. After state 45, state 53 is activated when condition 1.75 PIC <; CIC < 2.25 PIC is true, better than entering state 46 when .75 PIC < CIC < 1.25 PIC is true. After entering state 53, the state machine 12 resets the half symbol duration counter 14 and increments the data symbol counter 18. Also, the state machine 12 adjusts the LTC_data variable to a value of logical zero. This value is shifted simultaneously within the 64-bit offset register in one direction (first MSB or first LSB) dictated by the value of the address label ("FRONT" or "INVERSE"). State 54 is activated after state 51 and a verification of the value of account_token occurs at this time. When the account_square equals or exceeds sixty-four, state 55 is activated, which means a successful decoding (extraction) of the LTC framework. Otherwise, when the account_symbol is less than sixty-four, the state 37 is activated, whereby the state machine 12 causes the half-symbol counter 14 to start counting in the manner described above. The 10 LTC receiver has the ability to decode the bi-phase LTC coded data streams on any combination of the following operating conditions: • Front or reverse current directions. • Bit symbol rates from X / 30 to 80 * X, where X is the nominal frame speed LTC. Polarity of true and complementary data.

Inverse data streams can be generated when a linear audio tape track (not shown) storing the current LTC operates in the reverse direction. Bit-symbol rates other than nominal can be generated when the linear audio tape track storing current LTC operates in a shift mode. The bit-rate nominal speeds for various film or video frame rates are determined by Fs = 80 * Fr, where Fr is the film / video frame rate. In Table II below, a summary of the nominal, maximum and minimum bit symbol velocities is shown. TABLE II Due to the nature of the bi-phase mark modulation method, the transition polarity of the first bit of the synchronization word may differ from the LTC frame to the LTC frame depending on the number of logical zeros in the data. The 10 LTC receiver has the ability to decode currents of a true or complementary polarity. The foregoing describes a LTC frame receiver 10 having a fully digital implementation with the ability to operate with a high-speed clock that may not be synchronized with the bit symbol speed LTC.

Claims (15)

1. A method for decoding (extracting) a linear time code frame (LTC) of the type used in connection with film and LTC and the accompanying audio, characterized in that it comprises the steps of: (a) detecting a valid synchronization sequence within an incoming LTC frame, while measuring the predetermined symbol interval relative to a reference clock; (b) determine the direction of the LTC framework; (c) decoding the payload information of the LTC framework; Y (d) transfer the payload information in an order determined by the direction of the LTC framework.

The method according to claim 1, characterized in that the step of measuring the duration of the predetermined symbol interval comprises the step of measuring the clock periods of 27 MHz occurring within the duration of a bi-phase coded mark symbol interval within the LTC framework.

The method according to claim 2, characterized in that the duration step also comprises the step of extracting successive symbols from the LTC frame with the use of the 27 MHz clock periods as a reference.

4. The method according to claim 3, characterized in that the minimum symbol interval required for the 27 MHz clock is seventy.

5. The method according to claim 3, characterized in that the maximum allowable symbol interval for the 27 MHz clock is 210,497.

6. The method according to claim 1, characterized in that it also comprises the step of filtering each incoming LTC to remove a microcut.

The method according to claim 1, characterized in that steps (a) - (d) are repeated after receipt of each successive LTC frame.

8. An LTC receiver for decoding (extracting) a linear time code (LTC) frame of the type used in connection with film and television and the accompanying audio, characterized in that it comprises: a) a first means for detecting a valid synchronization sequence within an incoming LTC frame while measuring the predetermined symbol interval relative to a reference clock; b) a second means for determining the LTC frame address; c) a third means for decoding the payload information of an LTC frame; and d) a fourth means for transferring the payload information in an order determined by the direction of the frame LTC.

The LTC receiver according to claim 8, characterized in that the first means includes a first counter for measuring the duration of the predetermined symbol interval comprising the step of measuring the 27 MHz clock periods occurring within the duration of the a coded bi-phase mark symbol interval within the LTC frame.

The LTC receiver according to claim 8, characterized in that the second means includes a second counter for counting the synchronization pulses in the incoming LTC frame to establish a frame address LTC.

The LTC receiver according to claim 8, characterized in that the third means includes a data symbol counter for counting the symbols within an incoming LTC frame.

12. The LTC receiver according to claim 8, characterized in that the fourth means includes a state machine.

13. An LTC receiver for decoding (extracting) a linear time code (LTC) frame of the type used in connection with film and television and audio annex, characterized in that it comprises: a first counter for measuring a predetermined symbol interval relative to a reference clock; a second counter for counting the synchronization pulses within the incoming LTC frame; a third counter for counting the data symbols within the incoming LTC frame; a displacement record; and a state machine that responds to the accounts of the first, second and third counters to (a) detect a valid sequence of synchronization within an incoming LTC frame; (b) determining an LTC frame address; (c) decoding the payload information from the LTC framework; and (d) to transfer the payload information to the shift register in the order determined by the direction of the LTC frame.

14. The apparatus according to claim 13, characterized in that it further comprises a micro-cut filter for filtering the incoming LTC frame to remove the microcuts. The apparatus according to claim 13, characterized in that the first counter measures the predetermined symbol interval duration by measuring the 27 MHz clock periods occurring within the duration of a coded bi-phase mark symbol interval. within the LTC framework.