MXPA05011307A - Metodo de contabilidad y circuito logico para determinar utilizacion de recursos de procesador por hilo de ejecucion en un procesor simultaneo de multiples hilos de ejecucion (smt). - Google Patents

Metodo de contabilidad y circuito logico para determinar utilizacion de recursos de procesador por hilo de ejecucion en un procesor simultaneo de multiples hilos de ejecucion (smt).

Info

Publication number
MXPA05011307A
MXPA05011307A MXPA05011307A MXPA05011307A MXPA05011307A MX PA05011307 A MXPA05011307 A MX PA05011307A MX PA05011307 A MXPA05011307 A MX PA05011307A MX PA05011307 A MXPA05011307 A MX PA05011307A MX PA05011307 A MXPA05011307 A MX PA05011307A
Authority
MX
Mexico
Prior art keywords
threads
processor
thread
dispatching
accounting
Prior art date
Application number
MXPA05011307A
Other languages
English (en)
Spanish (es)
Inventor
Balaram Sinharoy
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MXPA05011307A publication Critical patent/MXPA05011307A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885—Monitoring specific for caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
MXPA05011307A 2003-04-23 2004-04-14 Metodo de contabilidad y circuito logico para determinar utilizacion de recursos de procesador por hilo de ejecucion en un procesor simultaneo de multiples hilos de ejecucion (smt). MXPA05011307A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/422,025 US7657893B2 (en) 2003-04-23 2003-04-23 Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor
PCT/GB2004/001586 WO2004095282A1 (en) 2003-04-23 2004-04-14 Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (smt) processor

Publications (1)

Publication Number Publication Date
MXPA05011307A true MXPA05011307A (es) 2006-01-30

Family

ID=33298778

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA05011307A MXPA05011307A (es) 2003-04-23 2004-04-14 Metodo de contabilidad y circuito logico para determinar utilizacion de recursos de procesador por hilo de ejecucion en un procesor simultaneo de multiples hilos de ejecucion (smt).

Country Status (14)

Country Link
US (3) US7657893B2 (enExample)
EP (1) EP1616259B1 (enExample)
JP (1) JP4536717B2 (enExample)
KR (1) KR100754153B1 (enExample)
CN (1) CN100458727C (enExample)
AT (1) ATE364204T1 (enExample)
BR (1) BRPI0409710B1 (enExample)
CA (1) CA2518468C (enExample)
DE (1) DE602004006858T2 (enExample)
ES (1) ES2286630T3 (enExample)
IL (1) IL171706A (enExample)
MX (1) MXPA05011307A (enExample)
TW (1) TWI291131B (enExample)
WO (1) WO2004095282A1 (enExample)

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Also Published As

Publication number Publication date
TW200504596A (en) 2005-02-01
DE602004006858D1 (de) 2007-07-19
KR100754153B1 (ko) 2007-09-03
CN1985242A (zh) 2007-06-20
US20120216210A1 (en) 2012-08-23
CN100458727C (zh) 2009-02-04
CA2518468A1 (en) 2004-11-04
IL171706A (en) 2011-03-31
US9003417B2 (en) 2015-04-07
CA2518468C (en) 2008-09-30
JP2006524380A (ja) 2006-10-26
TWI291131B (en) 2007-12-11
KR20060002842A (ko) 2006-01-09
EP1616259A1 (en) 2006-01-18
ATE364204T1 (de) 2007-06-15
BRPI0409710A (pt) 2006-05-02
US20100037233A1 (en) 2010-02-11
EP1616259B1 (en) 2007-06-06
US20040216113A1 (en) 2004-10-28
ES2286630T3 (es) 2007-12-01
US8209698B2 (en) 2012-06-26
WO2004095282A1 (en) 2004-11-04
BRPI0409710B1 (pt) 2020-01-14
JP4536717B2 (ja) 2010-09-01
US7657893B2 (en) 2010-02-02
DE602004006858T2 (de) 2008-02-14

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