MXPA01006868A - Interface interlace - Google Patents

Abstract

A method and system for communicating data between an integrated circuit (12) and each of a first device (14) and a second device (18). Communications between the integrated circuit and the first device use a first interface protocol, while communications between the integrated circuit and the second device use a second interface protocol. Both interface protocols, however, share the same data bus (22) and clock bus (24). To communicate using the second interface protocol, the first device, which uses the first interface protocol, is first deactivated by sending address data via the shared data bus that does not identify the first device, thereby causing the first device to enter an inactive state until a stop condition is detected on the shared data bus (22). Then, communications using the second interface protocol can be carried out, provided that a start or stop condition for the first interface protocol is not inadvertently generated on the shared data bus (22).

Description

INTERNET INTERCONNECTION.

BACKGROUND OF THE INVENTION. Technical Field of the Invention The present invention relates in general to interfaces for data communication in an integrated circuit environment and in particular to a method and system for communicating data on shared lines of bus configuration using multiple interfaces.

Description of Related Art Communications between integrated circuits and other devices in many applications use Intelligent Interconnect Communication (l2C), or inter-serial interface. -IC, developed by Philips Semiconductors. In the telecommunications industry, for example, mobile phones often use the l2C interface protocol for communication between the baseband controller, which is typically an application-specific integrated circuit (ASIC), and the LCD module. Other devices within the mobile phones also use the l2C interface protocol to receive data (including commands) from and transmit data to, the baseband controller. However, because the l2C interface is subject to certain patent protections, developers of LCD controllers and other controllers must normally obtain a license to be able to manufacture copiers that support the i2C interface protocol. As a result, the supply of external controllers that support I2C is often limited. With the development cycles that are increasingly shortened in the mobile telecommunications industry and other industries, that use of the I C interface protocol is not always in time to develop in a personalized way a controler that supports I2C. On the other hand, many of the external controllers support a serial point-to-point interface protocol that uses four lines: a data line, a clock line, a line specifying command data or display data and a chip line seiect. An alternative to having the development of a controller that supports l2C is to build the baseband controller or other ASIC to support the l2C interface protocol and the serial point-to-point interface protocol. Additional devices that can be added using either a driver that supports the l2C interface protocol or a driver that supports a serial point-to-point interface protocol, depending on cost availability and functional considerations. To support two interfaces, four I / Os (for each of the four serial point-to-point interface lines) are needed over the baseband controller. This requirement is problematic because the l / O pins add cost and require additional space. In addition, while systems that support multiple interface protocol use shared bus configuration lines that have been suggested, such systems are complex, inflexible and difficult to implement. There is therefore a need for a flexible and simplified system method that allows communications between an integrated circuit and one or more other devices that use a plurality of available interface protocols through shared bus configuration lines. The system must include a minimum number of pins i / O. Said method and system would allow, for example, the use of a controller that supports I2C, when available or a serial point-to-point controller, if an i2C controller is not available or if different capacities are desired. Furthermore, said method and system would allow the integrated circuit to selectively use different interface protocols depending on which protocol is supported by the device with which the integrated circuit is communicated.

BRIEF DESCRIPTION OF THE I NVENCÓN. The present invention comprises a method and system for data communication between an integrated circuit and a plurality of peripheral devices. The integrated circuit communicates with a first peripheral device using an I2C interface protocol and communicates with a second peripheral device using some other interface protocol. Nevertheless, both interface protocols share the same data bus configuration and clock bus configuration, thus reducing the number of pins required on the integrated circuit. Communications between the integrated circuit and the first peripheral device are achieved in accordance with the standard I2C interface protocols. Therefore, for communication with the first peripheral device, the integrated circuit transmits by means of the shared data bus configuration a unique I2C start condition followed by an address identification of the first peripheral device. The integrated circuit then transmits and the first device receives the data destined for the first device using the shared data bus configuration. The first device then responds with a recognition bit after each received bit. At the end of the data transmission, a single stop condition is transmitted. During such communications using the I2C interface protocol, the integrated circuit maintains a high voltage over a select chip bus configuration. This high voltage on the bus chip select configuration serves to inform the second peripheral device that communications are in operation and prevents the second device from interfering with said communications. On the other hand, when communications through interface l2C are not in operation, communications with the second peripheral device can be initiated. After a stop condition that is sent over the shared data bus configuration, the integrated circuit generates another start condition l C. However, this time the start condition is followed by an address that is not used by the first device. peripheral (or by any other l2C device attached), which causes the first device (and any other connected I2C devices) to enter an inactive state. Then, by removing the high voltage on the select chip of the bus configuration, the second device is activated and the data communications between the integrated circuit and the second device, by means of the shared data bus configuration can be executed, provided that none of the attached devices inadvertently transmit a start or stop condition, which could reactivate the attached C devices. Once the data communications are complete, the integrated circuit generates a stop condition on the shared data bus configuration, causing the joined l2C devices to start searching for a start condition again. Therefore, conditions using other interface protocols can be interleaved with I2C communications without requiring a data bus configuration and additional clock bus configuration, while simultaneously avoiding conflicts between two or more interfaces.

BRIEF DESCRIPTION OF THE DIAMETERS PC. For a more complete understanding of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawings in which: Figure 1 is a block diagram illustrative of an internal mobile phone circuit; Figure 2 is a representative diagram of the high voltage levels of the clock bus configuration, the data bus configuration and the select chip of the bus configuration of the circuits shown in Figure 1; and Figure 3 is a diagram of message flow operation and system operation illustrating a data transmission by means of an I2C interface and by means of a serial point-to-point interface.

DETAILED DESCRIPTION OF THE INVENTION Reference is now made to the drawings in which similar reference numbers refer to the same or similar parts through the different figures. Referring now to Figure 1, there is illustrated an illustrative block diagram of an internal circuit of mobile telephone 10. Typically, a mobile telephone includes a base controller 12; (i.e., an application-specific integrated circuit (ASIC) including a processor 13 to control the operation of the mobile telephone), and an LCD controller 14 (a l2C controller in this case) for command communication and data display to a LCD display module 16. The mobile telephone may also include other controllers 18 for communicating command data and other data to additional peripheral devices 20, such as a programmable electrically boring read-only memory. Communications over an I-C interface are carried out using two bidirectional bus configuration lines: a data bus configuration 22 and a clock bus configuration 24. The l2C interface uses a resistance concept in which the voltage level on the bus configuration 22 to 24 is raised when the bus configuration 22 to 24 is inactive or free. The same high voltage level is used to designate a logical "1" when the data bus configuration 22 is transmitting data. To designate a logical "0", a transmission device 12 or 14 connects the data bus configuration 22 to ground, causing the voltage over the entire data bus configuration 22 to reach zero. As a result, any controller l2C 14 can cause the voltage on the data bus configuration 22 to reach zero (ie by connecting the data bus configuration 22 to ground). To avoid the interruptions that may be caused if two devices 12 and 14 attempt to transmit data at the same time, a conflict resolution process is used. Essentially, by monitoring the voltage level of the data bus 22 during transmission of address or data, each transmission device 12 or 14, when attempting to transmit a "1", is able to detect if any other device 12 or 14 causes the voltage over the data bus configuration 22 to reach zero. The conflict is resolved by granting priority to the device 12 or 14 which is the first to transmit a logical "O" when the other device is transmitting a logical "1". In other words, the devices 12 or 14 that are the first to detect the presence of transmissions from another transmitting device 12 or 14 deliver control of the data bus configuration 22 to that other device 12 or 14. A communication on the interface l2C it is initiated by a unique "start condition", wherein the signal on the data bus configuration 22 goes from high to low while the clock line is in the high state (see figure 2). Continuing with the start condition, the transmission unit 12 or 14 sends the address of the receiving unit 12 or 14. All the units that do not identify their own address become inactive until a single "stop condition" (a low transition). at the top of the data bus configuration 22 while the clock bus configuration 24 is in the high state) is received. So, only the unit that is identified by the transmitted address that continues to receive data. To ensure that the device is receiving data, the receiving unit 12 or 14 transmits an acknowledgment bit, defined by a logical level "0", after the reception of each bit. According to the present invention, another interface protocol is "interconnected" with the interface l2C which uses the same data bus configuration 22 and clock bus configuration 24 as the interface l2C. In one embodiment, the "interconnected" protocol is a serial point-to-point interface protocol.

Alternatively, a Serial Peripheral Interface (SPI) protocol or some other interface protocol can also be used. Although the following description and figures focus on the use of a serial point-to-point protocol as an example of the invention, it will be understood by those skilled in the art that other protocols may also be interconnected with the IC protocol. After the start condition is generated, the baseband controller 12 (or some other device that wishes to communicate through the serial point-to-point protocol) transmits an address that is not used by any of the l2C 12 units or 14 connected to the data bus configuration 22. Following the address transmission, a recognition bit can also be transmitted by the same device. As a result, all the connected I2C units go into the inactive state, and the data bus configuration 22 and the clock bus 24 configuration can be used to transmit according to a serial point-to-point interface protocol (or some other protocol). interface). The baseband controller 12, for example, can send point-to-point data by means of the data bus configuration 22. In this case, the transmitted data is designated as command data or as display or user data by a signal on the command / display bus configuration 26. During serial point-to-point data transmissions, any unintentional generation of a start or stop condition must be avoided to prevent the l2C units from returning to an active state. Therefore, the serial point-point units 18 and the baseband controller 12 must avoid a high-to-low transition or a low-to-high transition over the data bus configuration 22 when the clock bus configuration 24 is in the been elevated. In addition, serial point-to-point interfaces generally do not maintain a high voltage when they do not transmit data. Instead, serial point-to-point interfaces must drive the data line to a high voltage to transmit a logical "1" and drive the data line to a lower or negative voltage to transmit the logical "0" . Because the I2C interfaces use the concept of resistance, the controllers 18 that support the protocol of the serial point-to-point interface must maintain a high impedance during the operation under protocol I C to prevent said controllers from causing the alteration of any transmission that is in process on the data bus configuration 22. This three state condition is controlled by an activation signal on the chip of the bus configuration 18. Therefore, when the system 10 is operating under a point interface protocol At the serial point, the bus configuration chip 28 is set high, thus allowing serial point-to-point drivers 18 to operate in their normal form. On the other hand, the select chip of the bus configuration 28 is set low when the system 10 is using the interface protocol l2C, causing the serial point-to-point drivers 18 to maintain the high impedance to prevent interference with the l2C communications. As those skilled in the art will appreciate, however, the arrangements on the select chip of the bus configuration 28 can be reversed or other signaling methods can be used on the select chip of the bus configuration 28 to indicate when the general system 10 is using the interface protocol l2C and when the system 10 is using the serial point-to-point interface protocol (or some other). Referring now to Figure 2, a representative diagram of the voltage levels on the clock bus 24 configuration, the data bus configuration 22, and the select chip of the bus configuration 28 of the circuits shown in Figure 1 are shown. . At time zero (T = 0), the baseband controller 12 generates a start condition causing the voltage over the data bus configuration 22 to go from high to low while the voltage over the clock bus configuration 24 is high. As a result, each of the l2C 14 controllers that are connected to the baseband controller 12 start looking for their unique address. A 7-bit address is transmitted during the next 7 clock cycles (ie, T = 1 to T = 7 (not shown specifically)). Alternatively, a 10-bit address can be sent, depending on the type of I2C interface being used. However, in this example, the address transmitted by the baseband controller 12 does not identify any of the linked l2C 14 controllers. The transmission of an unused address causes the l2C 14 controllers to enter the idle state, allowing this so that the baseband controller 12 (or some other serial 18 point-to-point controller) transmits data using a serial point-to-point interface protocol (or some other interface protocol) while all the l2C 14 controllers are in an inactive state. As mentioned before, it is important that the baseband controller 12 and other devices 18 that support the serial point-to-point interface protocol avoid unintentional generation of a start or stop condition through point-to-point communication. serial point. In addition, during the transmission of the start condition and the address data, the serial point-to-point controllers 18 must maintain high impedance to avoid any interference with the l2C communications. Before initiating serial point-to-point communications, the serial point-to-point controllers 18 must be informed that the data bus configuration 22 is available for serial point-to-point communications. Therefore, the baseband controller 12 loads the seiect chip of the bus configuration 28 by activating the reception of the serial point-to-point controller 18 to receive data, starting after the transmission of the first address bit as specified in the standard. l2C in the ninth clock cycle (T = 9) in this case. The baseband controller 12 then transmits and the receiving controller 18 receives a string of binary data (i.e. logical 0 at T = 9, logical 1 at T = 10, logical 0 at T = 1 1, and so on ). After the data transmission is completed, the select chip of the bus configuration 28 is deactivated, causing the serial point-to-point drivers 18 to return to an inactive / high impedance state. In addition, the baseband controller 12 generates a stop condition in one clock cycle after the data transmission is complete (at T = 15 in this case). The generation of a stop condition causes the joined l2C units 14 to return to an active state, in which they again start searching for a start condition (starting at T = 16). Referring now to Figure 3, there is illustrated a message flow diagram and system operation illustrating a data transmission by means of an I2C interface and by means of a serial point-to-point interface. To initiate a data transfer over the interface l2C, the baseband controller 12 generates a start condition in step 50, which causes a start signal l2C 52 which is sent over the data bus configuration 22 to all the united controllers 14 and 18. In response to the start signal 52, the attached l2C controllers 14 search their respective directions in step 54. Starting with the next clock cycle after the start condition, the baseband controller 12 transmits an address signal 56 that contains the unique address of an LCD controller 14 that supports the interface protocol l2C. As a resultany attached devices 14 that support l2C and that are not identified by the transmitted address go into an inactive state, while the addressed LCD controller 14 transmits a recognition bit signal 57 over the data bus configuration 22 to inform the controller of baseband 12 that is ready to receive data and then begins to search for the data in step 58. The baseband controller 12 begins to transmit a data signal l2C 60. In addition, after receiving each byte of the signal of data l2C 60, the receiver LCD controller 14 transmits a recognition bit signal 62 over the data bus configuration 22 to inform the band controller 12 that the data was received. Once the I2C data message is complete, the baseband controller 12 generates a stop condition in step 64, which causes a stop signal 66 that is transmitted along the data bus configuration 22 to all attached devices 14 and 18. Immediately upon receipt of stop signal 66, all joined I2C units 14 begin to monitor data bus configuration 22 for a start condition in step 68. To initiate another data transfer (this time using a serial point-to-point interface protocol), the baseband controller 12 again generates a start condition in step 50 ', causing the start signal 52' to be sent to all units 14 and 18 united. Therefore, I2C units 14 start to search again for their respective addresses in step 54 '. However, in this case, the baseband controller 12 transmits an address signal 70 that contains an address that is not used by any of the joined I2C units 14. As a result, all the attached I2C units 14 enter a state inactive in step 72. The baseband controller 12 then sets the select chip line in step 74, sending a select 76 signal to all connected serial point-to-point controllers 18. In response to the chip signal select, in step 78 the serial point-to-point controllers 18 leave the high impedance state, which is used by those controllers 18 during the I2C operations, thus allowing the controllers 18 to receive serial point-to-point data . The baseband controller 12 then sends the serial point-to-point interface data signal 80 to the receiving unit 18. After the data signal 80 is complete, the baseband controller 12 deactivates the chip select line in step 82 causing the serial point-to-point controllers 18 to return to the inactive / high impedance state in step 84 and generate a stop condition in step 64 '. The resulting stop signal 66 'causes the I2C units 14 to begin to monitor the data bus configuration 22 again for a start condition (see step 68). Although a preferred embodiment of the method and apparatus of the present invention has been illustrated in the accompanying drawings and is described in the above detailed description, it is understood that the invention is not limited to the described embodiment, but is capable of numerous rearrangements, modifications and substitutions without departing from the invention as set forth and defined by the following claims.

Claims (34)

1. CLAIMS 1. A method for data communication between an integrated circuit and a plurality of other devices, wherein the integrated circuit uses a first interface protocol for communication with a first device and a second interface protocol for communication with a second device, comprising the stages of: transmitting data intermittently between the integrated circuit and the first device by means of a shared data bus configuration using the first interface protocol, the shared data bus configuration connected to the integrated circuit, the first device and the second device; disable communications that use the first interface protocol; and enabling communications using the second interface protocol while communications using the first interface protocol are deactivated, the method characterized by the steps of: providing a clock signal by means of a shared clock bus configuration, shared clock bus configuration connected to the integrated circuit, the first device and the second device, wherein the data transmission between the integrated circuit and the first device is executed according to the clock signal on the shared clock bus configuration; and transmit the data between the integrated circuit and the second device by means of the shared data bus configuration using the second interface protocol, the data transmitted between the integrated circuit and the second device according to the clock signal on the bus configuration of shared clock, wherein the data transmission stage they use in the second interface protocol is executed without reactivating the communications using the first interface protocol.
2. 2. The method according to claim 1, characterized in that the first interface protocol comprises Intelligent Intercommunication Communication. The method according to claim 2, characterized in that the step of deactivating the communications using the first interface protocol comprises the steps of: generating a start condition signal on the shared data bus configuration; and transmitting a selected address over the shared data bus configuration, wherein the selected address is not used by any intelligent interconnect communication device connected to the shared data bus configuration. The method according to claim 3, characterized in that the step of intermittently transmitting data between the integrated circuit and the first device further comprises the steps of: generating a start condition signal on the shared data bus configuration; transmitting an address of the first device over the shared data bus configuration; send data through the configuration of a shared data bus from the integrated circuit to the first device; and generating a stop condition signal on the shared data bus configuration. 5. The method according to claim 3, characterized in that the second interface protocol comprises a serial point-to-point interface protocol. The method according to claim 3, characterized in that the step of enabling communications using the second interface protocol comprises sending a second interface activation signal by means of a chip-select line. The method according to claim 3, characterized in that the second interface protocol comprises a serial peripheral interface protocol. The method according to claim 3, characterized in that the integrated circuit comprises a baseband controller in a mobile telephone. 9. The method according to claim 8, characterized in that the first device comprises an LCD controller. ^ 10. The method according to claim 3, further comprising the step of reactivating the com- munications using the first rate protocol after completing the transmission of data between the integrated circuit and the second device. eleven . A system for data communication comprising: an integrated circuit having at least one data pin and a clock pin, the data pin coupled to a shared data bus configuration, wherein the integrated circuit is adapted to support a first interface protocol and a second interface protocol; a first controller adapted to support the first interface protocol, the first controller coupled to the shared data bus configuration for communicating data between the integrated circuit and a first device by means of the shared data bus configuration using the first interface protocol; and a second controller adapted to support the second interface protocol, the second controller coupled to the shared data bus configuration to communicate data between the integrated circuit and a second device by means of the shared data bus configuration using the second interface protocol , the system characterized by: the clock pin coupled with a shared clock bus configuration, the data communication between the integrated circuit and the first device and between the integrated circuit and the second device executed using clock signals received by means of the shared clock bus configuration, wherein the integrated circuit is adapted to disable the first controller by sending a deactivation signal on the shared data bus configuration, to activate the second controller to execute communications between the integrated circuit and the second device, and to transmit data to ha ia the second device using the second interface protocol without generating a reactivation signal to reactivate the first controller. The system according to claim 1, characterized in that the first interface protocol comprises intelligent interconnection communication. The system according to claim 12, characterized in that the second interface protocol comprises a serial point-to-point interface protocol. The system according to claim 12, characterized in that the second interface protocol comprises a serial peripheral interface protocol. 15. The system according to claim 12, characterized in that the first controller comprises a controller LCD The system according to claim 12, characterized in that the integrated circuit is adapted to deactivate the first controller by sending an address that is not associated with the first device. 17. The system according to claim 12, characterized in that the integrated circuit is adapted to activate the second controller using a chip-select line. 18. The system according to claim 12, characterized in that the integrated circuit is adapted to reactivate the first controller by sending a stop condition on the shared data bus configuration after completing the transmission of the data to the second device. The system according to claim 12, characterized in that a baseband controller for operating in a mobile telephone includes the integrated circuit, and the second interface protocol comprises a serial data interface protocol different from the communication protocol of Intelligent Interconnection, further comprising: a chip chip select to transmit an activation signal by means of a chip select line to activate the serial data interface of the second controller; and wherein the integrated circuit is further adapted to control the activation signal. The system according to claim 19, characterized in that the integrated circuit is adapted to deactivate the intelligent interconnect communication data interface of the first controller by transmitting an address that is not associated with the first controller. 21. A method for data communication between an integrated circuit and a plurality of other devices, wherein the integrated circuit uses a first interface protocol for communication with a first device and a second interface protocol for communication with a second device, which it comprises the steps of: transmitting the data intermittently between the integrated circuit and the first device by means of a shared data bus configuration using the first interface protocol, the shared data bus configuration connected to the integrated circuit, the first device and the second device; deactivating communications that use the first interface protocol; and enabling the communications using the second interface protocol while the communications using the first interface protocol are deactivated, the method characterized by: the deactivation of communications using the first interface protocol executed by the steps of: generating a start condition signal, on the shared data bus configuration; and transmitting a selected address over the shared data bus configuration, wherein the selected address is not used by any device that employs the first interface protocol and is connected to the shared data bus configuration; transmitting data between the integrated circuit and the second device by means of the shared data bus configuration using the second interface protocol, wherein the stage of transmitting data using the second interface protocol is executed without reactivating the communications using the first interface protocol. 22. The method according to claim 21, characterized in that the first interface protocol comprises Intelligent Interconnect Communication. The method according to claim 21, characterized in that the step of transmitting data intermittently between the integrated circuit and the first device further comprises the steps of: generating a start condition signal on the shared data bus configuration; transmitting a first device address on the shared data bus configuration; send data via the shared data bus configuration from the integrated circuit to the first device; and generating a stop condition signal on the shared data bus configuration. 24. The method according to claim 21, characterized in that the second interface protocol comprises a serial point-to-point interface protocol. 25. The method according to claim 21, characterized in that the step of enabling the com- munications using the second interface protocol comprises sending a second interface activation signal by means of a chip select line. 26. The method according to claim 21, characterized in that the second interface protocol comprises a serial peripheral interface protocol. 27. The method according to claim 21, further comprising the step of reactivating communications using the first interface protocol after completing data transmission between the integrated circuit and the second device. 28. A system for data communication comprising: an integrated circuit having at least one data pin, the data pin coupled to a shared data bus configuration, wherein the integrated circuit is adapted to support a first protocol of Interface and a second interface protocol; a first controller adapted to support the first interface protocol, the first controller coupled to the shared data bus configuration for communicating data between the integrated circuit and a first device through the shared data bus configuration using the first interface protocol; and a second controller adapted to support the second interface protocol, the second controller coupled to the shared data bus configuration to communicate data between the integrated circuit and a second device by means of the shared data bus configuration used by the second protocol by interface, the system characterized by: the integrated circuit adapted to deactivate the first controller by transmitting over the shared data bus configuration of an address not associated with the first device, to activate the second controller to execute communications between the circuit integrated and the second device and to transmit data to the second device using the second interface protocol without generating a reactivation signal to reactivate the first controller. 29. The system according to claim 28, characterized in that the first interface protocol comprises Intelligent Interconnection Communication. 30. The system according to claim 29, characterized in that the second interface protocol comprises a serial point-to-point interface protocol. 31. The system according to claim 29, characterized in that the second interface protocol comprises a serial peripheral interface protocol. 32. The system according to claim 29, characterized in that the first controller comprises an LCD controller. 33. The system according to claim 29, characterized in that the integrated circuit is activated to activate the second controller using a chip-select line. 34. The system according to claim 29, characterized in that the integrated circuit is adapted to reactivate the first controller by sending a stop condition on the shared data bus configuration after completing the data transmission to the second device.