ARRANGEMENT OF VERTICAL CIRCUITS INTEGRATED FIELD AND BACKGROUND OF THE INVENTION The invention relates to a vertically integrated circuit arrangement according to claim 1, the current manufacturing procedures in the semiconductor art and new technologies continuously lead to a miniaturization of structures made with them. The miniaturization is largely based on a dwarfing of the width of the channels of the MOS transistors, so that the area needed for a constructive element decreases quadratically, with this we have already reached structures with a channel width of 0.35μm, and smaller (0.25 mm), it is nevertheless appreciable that structures of a size of O.lμm can be used. With a semiconductor structure that becomes smaller, the danger of the effects of external disturbance grows exponentially to miniaturization. Such external disorders can be precipitated, for example, by particles that can be captured in quantum mechanics. The particles pass through the box surrounding the arranged circuit arrangements and integrated into the so-called semi-conductor chip cards and not only lead to the damage of the semiconductor structures built there, but also lead to the generation and absorption of electrons, with this can be caused an operation with -fallas either continuous or intermediate semiconductor structures. The likelihood of such external effects causing disturbances grows as semiconductor structures leave the earth's atmosphere as is common in the space travel technique. In these applications, electronic circuits usually jacketed with gold foils and pla: a are used to cause at least some absorption of the aforementioned particles. When miniaturization is increased, it can not be prevented, however, that also the aforementioned jacketing with gold and silver sheets does not guarantee any sufficient protection, so that the danger from the penetrations described generates consequent effects. This danger also increases in usual terrestrial application. SUMMARY OF THE INVENTION The present invention proposes the task of providing integrated circuit arrangements that also guarantee safe operation in applications in the space travel technique. DESCRIPTION OF THE INVENTION This task is solved according to the invention by an arrangement according to claim 1, in that way a vertically integrated circuit arrangement is provided by means of an identical functionality to at least two integrated circuits one on the other and to a control installation that is available with redundancy for safe operation and thus guaranteeing a higher safety performance. In another advantageous embodiment as indicated in claim 2, this is supported by the control facility obtaining redundant functionality from a statistical result. By means of the arrangement described above, it is possible to distribute relevant processes in data processing security by means of the control installation, either accidentally or searched in circuits or integrated connections one on the other, so that prevents processes of an undesirable grip on relevant safety data. Next, an example of an embodiment will be explained with reference to the figure, in whan example of an embodiment according to the invention shown schematically in a cross section is shown. As shown in the figure, at least two integrated circuits according to the invention are provided whare constructed of two semiconductor cards 1 and 2, one on top of the other. The semiconductor chips 1 and 2 have, on one of their surfaces, an active zone, 2a, in whthe integrated connections are constructed with a conventional technology. With this the represented arrangement can as a whole work as a vertically integrated circuit array, providing contacts that in the figure are only represented in an exemplary manner, but that are built with the necessary number. Here, the active zones la, 2a, contact positions one over the other Ib, 2b. In the semiconductor chip l, a through opening 7 has been made, which is filled by a conductive material 6, and in this way the contacts 1 and 2b are joined together. In addition, the two semiconductor chips 1 and 2 present, in their corresponding active zones 2a, a widely identical functionality, this being constructed in the form of an integrated circuit. In at least one of the active zones of the two semiconductor chips, a control installation not shown is additionally provided. This controls the joint work between the two circuits and connections integrated in the two semiconductor chips 1 and 2. There are basically two different procedures here that are also combinable with each other. Next, the first way to proceed will be described. If, for example, data processing processes are found in the two semiconductor chips, which, as described above, have identical functionality and are in parallel, then the control installation obtains from the two processes that run in parallel a statistical result, this has is part of an accidental disorder by intromission of particles, a high probability. The probability is increased additionally by establishing more than two semiconductor chips one on top of the other. Since, as indicated above, the influence on electronic behavior by particle intrusion can also be present to a large extent on the ground, the arrangement described above can also be applied in full meaning to relevant safety circuits. These find applications especially as special constructive parts in the so-called "chip cards, Chip-Cards" or "Smart-Cards", or also as basic constructional parts in reading apparatuses for the aforementioned arrangements. In these applications, relevant security data, such as keywords, should be increasingly protected against an unauthorized attack. This can therefore be done that the development or use of this relevant safety data, only takes place on a semiconductor chip, which is covered by another, this is done according to the figure because the relevant safety data are only made in the semiconductor chip 2. It is also provided that the integrated circuit or connection that is not represented individually, divide the work of the other integrated circuits with equal functionality according to a determined process form in the control installation arranged in one of the active zones la, 2a, of the first or second semiconductor chip. Since the functionality of both is the same, it can not be obtained by an analysis of the circuit in which the processes take place in the semiconductor chip l, or in the semiconductor chip 2, in addition it is provided that the control installation is covered by a development of accidental control data, for example in the semiconductor chip 1, or in the semiconductor chip 2. Since in this way it is not predictable in which of the integrated circuits certain processes are carried out, the analysis of the data to be performed Making is very difficult.