MXPA00005999A - High speed data bus driver - Google Patents

Abstract

Information is coupled to a data bus such as an I2C data bus using a push-pull circuit. The push-pull circuit provides for communicating on the data bus at two different data rates. The push-pull circuit includes an active pull-up device that is enabled during a first push-pull mode of operation for providing a high data rate. During a second normal mode of operation, the active pull-up device is disabled providing a low data rate. When the active pull-up device is deactivated, the clock and data buses are driven by the external resistors connected thereto at a data rate lower than the data rate during the first mode.

Description

U N IDAD D E BAR BAR CO C LECT RA D E DATE S HIGH VE LOCI DAD CAM PO D E I NVENTION The present invention involves digital data busbar systems.

BACKGROUND OF THE INVENTION Systems such as electronic consumable systems typically encompass different devices, such as integrated circuits, which are coupled together using data bus bars to communicate information between devices. An example of this type of system is a television receiver, which includes a series data bus 12C to communicate the tuning data from a control microprocessor to a tuner which causes the tuner to tune to a particular channel. A busbar 12C is a well-known serial data bus comprising two bus lines, a clock line designated SCL and a serial data line designated as SDA, which carry the information between the devices connected to the bus collector Each device is assigned to a single address which allows communications in the busbar to be directed to a particular device. Each device can transmit data, receive data, or both as required by the function of the device.

In addition to transmitting and receiving data, each device can also function as a master device or slave device when performing data transfers. A master device is a device that initiates a data transfer in the bus bar and generates clock signals that allow that transfer. At that time, any directed device is considered a slave device. The busbar 12C is a multiple master bus, which means that the busbar can be controlled with more than one device. The main devices are usually control devices such as microprocessors, microcomputers or microcontrollers (also referred to herein as "controllers"). The possibility of connecting more than one microcontroller to the busbar means that more than one master device can attempt to start the data transfer at the same time in the busbar. A process known as arbitration solves that event favorably. The arbitration is based on a wired AND connection of all the 12C interfaces to the busbar. If the case occurs in which two or more main devices try to place information in the bus, the first to produce a logical one, will lose the arbitration, when the other produces a logical zero. The clock signals during the arbitration are a synchronized combination of the clocks generated by the main devices that use a wired AND connection with the SCL line. The specification for the busbar protocol 1 C specifies that the output stages of the devices connected to the busbar must have an open drain or an open collector in order to perform the wired AND function. As a result, positive coupling of the busbar lines is achieved through the positive coupling resistors connected between the busbar lines and a voltage supply source. The generation of the clock signals in the busbar 12C is always the responsibility of the main devices. Each master device generates its own clock signal when it transfers the data in the busbar. The data is valid only during the high logic period of the clock. The clock signals of the busbar from the master device can only be altered by another master device when arbitration occurs or when the clock signals are lengthened by a slow slave device that keeps the clock line low. For example, every byte of information put on the SDA line (ie, 8 bits of information) must be followed by a recognition bit. A. clock pulse related to recognition is generated by the master device. During the clock recognition pulse, the transmitter releases the SDA line and the receiver must connect the SDA line to negative: A receiving device can delay reception by another data byte, for example, until another function has been performed. how to generate an interruption, by keeping the SCL clock line low, which will force the transmitting device to enter a wait state. U.S. Pat. U U No. 4,689,740, granted to Adrianus P. M. M. Moelands and Herman Schutte details the operation of the 12C busbar and its protocol.

BRIEF DESCRIPTION OF THE INVENTION The invention resides, in part, in recognizing that while the relative simplicity and availability of many compatible devices make the bar protocol 12C a desirable protocol, the shape of a busbar unit with the protocol of The busbar is not always suitable for certain applications. For example, busbar units that are used with a busbar system 12C typically use an open collector (or drain) device with a positive-coupled resistor coupled between the busbar line and a reference voltage source. . The capacitive load of a busbar line combined with the resistance of a positive-coupled resistor can significantly degrade the speed at which the busbar line can be coupled to positive. In addition, the capacitive load increases with the number of devices coupled to the busbar. This can be a problem for applications that require high speed and involve high capacitive loads such as during the testing of a device that incorporates the capacity of the busbar unit (note that the term "device", as in use within this, includes integrated circuits and devices such as television receivers). In addition, the master device has many other functions to play in addition to communicating with slave devices. Therefore, there is a need for a busbar unit suitable for driving the busbar as a busbar 12C with large loads at high speed to perform communication between the master device and the slave devices as fast as possible. In addition, the inventor has recognized that by using a modified form of the busbar unit that can drive large loads at high speed they may be incompatible with the current compatible busbar devices. In particular, existing compatible 12C devices are designed with a sufficient current build-up capability to neatly connect a bus line maintained high by a positive-coupled resistor (e.g., during a recognition interval or to cause a waiting status). This current accumulation capability may be inadequate for coupling a busbar line driven by a high speed drive circuit to negative. Also, the inventor has recognized that while it is desirable to communicate data at high data rates through a heavily loaded bus bar, doing so can have undesirable effects of noise. By pushing data through a data bus at high data rates, it involves using fast signal ends that have high frequency harmonic components. For example, in a television system, these • High frequency harmonics can introduce noise into the signal video that processes the channel and can cause undesirable noise effects in the presented video image. The invention also resides, in part, in providing an apparatus for coupling the data in a data bus that solves the problems described above. More specifically, the • The apparatus constructed in accordance with an aspect of the invention comprises a data bus, a passive device for changing a signal in the data bus between a first and second states at a first speed during a first mode of operation and a active device enabled for a second operation mode for changing the signal between the first and second states at a second speed different from the first speed. The second mode of operation may correspond to a particular condition of the busbar, such as a recognition condition or a data reading condition. In accordance with another aspect of the invention, the information generated by a device is coupled to a data bus 12C by means of a push-pull device. Another aspect of the invention involves a push-pull device having first and second modes of operation. During the first In the mode of operation, the push-pull device couples the information with the data bus 12C at a first speed. During the second mode of operation, the counterphase device couples the information with the data bus 12C at a second speed. According to another aspect of the invention, the apparatus comprises a coupling device for coupling the data with a data bus and a time signal generator for generating a time signal indicating the first and second portions of a data signal. TV. The coupling device is controlled by a device by a control device that responds to the time signal so that the coupling device couples the data with the bus at a first speed during the first portion of the television signal and couples the data in the data bus at a second speed during the second portion of the television signal. The first portion of the television signal may comprise an active video interval while the second portion of the television signal may comprise a blocking interval. The first speed at which the data is coupled with the data bus may be less than the second speed at which the data is coupled with the bus. A push-pull device located in the coupling device can be disabled during the first portion of the television signal and enabled to push the data into the bus at the second speed during the second portion of the television signal.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood with reference to the drawings, in which: Figure 1 shows, in the form of a schematic diagram, an arrangement of the main and slave devices communicating through the bus bar data; • Figures 2A through 2D show the time diagrams illustrating the operation of the system shown in Figure 1; Figure 3 shows, in the form of a schematic diagram, a mode of the data bus communication system for data communication between the main devices 15 and slave according to the present invention; Figure 4 shows, in the form of a schematic diagram, an embodiment of a portion of the system shown in Figure 3; and Figures 5A through 5D show time diagrams illustrating the operation of the system shown in Figure 3.

DETAILED DESCRIPTION OF THE INVENTION Within a conventional data bus system such as the busbar system 12C shown in Figure 1, the The main device 2 is connected to the slave device 4 (designated Slave # 1) by means of a busbar 6 12C. In accordance with the bus bar 12C conventions, the SDA and SCL tags are used to identify the serial data line and the clock line, respectively in the busbar modes 12C described herein and shown in the drawings. Accompanying figures. The main device 2 comprises a unit for driving each line of the busbar. More specifically, the bus SCL and SDA lines in Figure 1 are driven using bipolar NPN transistors 8 and 10, respectively, connected thereto. The base of each transistor 8 and 10 is connected to an output of a respective inverter 11, 12. A respective impulse signal, IMPULSO SCL and IMPULSO SDA; it is coupled with the input of a corresponding inverter 11, 12. When the IMPULSE SCL or PULSE SDA signals are at a high logic level, the respective NPN transistors 8 or 10 do not turn on causing the SCL and SDA lines to be coupled to positive at a higher level, ie, at 5 volts on the Figure 1, by the resistors Rc and RD of coupling to positive, respectively. When the signals of PULSE SCL or PULSE SDA are at a low logic level, the respective NPN transistors 8 or 10 are turned on to positively connect their respective bus lines to a low level, for example, a circuit with return through Earth in Figure 1.

The slave device 4 has a negative coupling device, implemented in Figure 1 as a bipolar NPN transistor 13 with a base terminal that is connected to the output of the inverter 14. The transistor 13 couples the SDA line to negative on reception a logical signal high in its base. The input of the inverter 14 is coupled to receive the "Read data" signal. The negative coupling of the SDA line by the transistor 13 occurs when the data is read from the slave device 4, for example, the "Read data" entry is switched between high and low. The data received by the slave device 4 from the lines of the busbar SCL and SDA are coupled with the logical receiver that processes the data. The positive coupling resistor of the SCL line is designated as Rc and the positive coupling resistor of the SDA line is designated RD. Each positive coupling resistor is shown connected at one end to an exemplary voltage supply of 5 volts and to a respective capacitor Cc or CD, representative of equivalent concentrated capacitances of a respective busbar line. The SDA and SCL busbar lines are also connected to other slave devices as indicated in Figure 1. The SDA line is bidirectional while the SCL line is only an output from the master device that generates the clock signal, ie device 2 in Figure 1.

Figures 2A through 2D illustrate the relative time diagrams of the IMPULSE SCL signal, the signal present on the SCL line, the PULSE SDA signal and the signal present on the SDA line, respectively. The signals of PULSE SCL and PULSE SDA are the pulse signals coupled with the busbar lines SCL and SDA, respectively, by means of a coupling device such as devices 8, 11 and 10, 12 of busbar units of the Figure 1. A nine-bit transmission, including a recognition bit, is illustrated in Figures 2A through 2D by the waveforms for the IMPULSE signals SCL, SCL, PULSE SDA and SDA. A solid line portion of the waveform for the SCL signal is labeled "Low Cc" and shows the waveform of the signal on the SCL line that results from the low capacity load on the SCL line. The dotted portion of the SCL waveform, labeled "high Cc" indicates the signal waveform on the SCL line that results from a high capacity load on the SCL line. Similarly illustrated, there is an SDA line with low capacity load (the solid line portion of the SDA waveform is labeled "low CD") and an SDA line with high capacity load (the dotted portion of the line) of the SDA waveform is designated "high CD"). The state of the data (logical 0 and 1) during the recognition interval (represented by the generation of a clock recognition pulse by the master device, release of the SDA line by the transmitter and the negative coupling of the SDA line by the receiver during the clock recognition pulse) is also illustrated in Figures 2A through 2D. Figure 3 illustrates the apparatus for impuing the busbar in accordance with the principles of the present invention. To provide higher data rates in bus lines with heavy load, for example, to allow high speed production tests, Figure 3 illustrates a system for decreasing the slow rise times associated with high capacity loads in a bus line In particular, the busbar unit within the main device 2 includes separation devices 15 and 16, which provide the coupling to positive and negative coupling of the lines of the busbar. More specifically, the three-state separators 15 and 1 6 drive the respective bus lines SCL and SDA in a high-speed mode that should be called as a push-pull mode. It is also possible to operate the busbar in a conventional manner (for example, in a low speed mode by means of passive positive coupling resistors). However, in the push-pull mode, the separators 15 and 16 of three states are always in an active state and the bus lines are driven at a high logic level in a faster way, compared to the conventional mode, to through relatively large source currents adapted by the separators of three states.

The separators of three states such as separators 15 and 16 of Figure 3 can be implemented as shown in Figure 4. Although Figure 4 shows a modality using the field effect transistors, different technologies can be used, among which bipolar and field effect transistors are counted, to implement the units shown. In Figure 4, the drain terminals of transistor 7 PMOS and transistor 18 N MOS are coupled together. The source terminal of the transistor 17 is coupled to a supply voltage, for example 5 volts, and the source terminal of the transistor 1 8 is coupled to a reference potential, for example, to ground. The gate terminal of the transistor 17 is coupled to the output of the gate NAN D having as input signal INPUT; which represents the data that will be driven on the busbar and the signal ENABLED. The gate terminal of the transistor 18 is coupled to the output of the gate 32, which has as input signal INPUT and a reverse version of the signal HAB I LITATED (inverted by the inverter 30). When the signal HABI LITADO is high (in logical 1), "the separator is enabled to transmit the data. Specifically, when enabled, the logical 0 values in the INPUT signal pass through gate 32 Ñ R and transistor 1 8 to the bus (OUT signal) while the logical values 1 in the INPUT signal pass to through gate 34 NAN D and transistor 1 7 to the bus bar.

Returning to Figure 3, the MODE PP signal (push-pull mode) is generated with a microprocessor 27. The microprocessor 27 decides whether to generate a PP mode signal of high or low logic level, which will determine whether the main device 2 operates in way in contrafase or normal. The MODE PP signal is coupled to an input of the NAND gate 22 through the inverter 20. The PULSE SCL signal is also generated by the microprocessor 27 and is coupled to the other input of the NAND gate 22. The output of the NAND gate 22 provides the ENABLED signal for the three-state separator 15, so that the separator 15 is always enabled when the MODE PP signal is at a high logic level. The busbar line SCL is positively coupled to a high logic level by the active device in the three-state separator 15 in connection with a high-logic IMPULSO SCL signal while the three-state separator is enabled, this represents a first state. The line of the busbar SCL is coupled to negative at a low logic level by the separator 15 of three states in connection with a signal IMPULSO SCL logic, low while the separator 15 of three states is enabled, this represents a second state. The three-state separator 15 is always enabled to drive the bus line SCL and change the line SCL between the first and second signal states (logical levels high and low) when the signal MODE PP is at a high logic level.

In order to use the push-pull mode to achieve a high logic level in the SDA bus bar line, the main device 2 must not be reading data from the directed slave device nor must it be generating a clock SCL pulse for the bit recognition generated by the slave device. The MODE PP signal is also coupled to an input of the NAND gate 23 via the inverter 21. The PULSE SDA signal is also generated by the microprocessor 27 and is coupled with the other input of the NAND gate 23. The output of the NAND gate 23 provides the signal enabled for the three state separator 16, so that the separator 16 is always enabled when the MODE PP signal is at a high logic level. The SDA busbar line is positively coupled to a high logic level by the active device included in the three-state separator 16 in connection with a high logic SDA PULSE signal while the SDA busbar line is coupled to negative to a low logic level by means of the separator 16 of three states in connection with a signal PULSE SDA logic low while the sewer 16 of three states is enabled. When the main device 2 is in a reading cycle or during a recognition interval, the microprocessor 27 will generate a low logic PP MODE signal and the separators 15 and 16 will be disabled when the PULSE signals SDA and SCL, respectively, are at a high logic level. In this case the busbars SDA and SCL are operating in a normal mode coupled to positive by the external resistors Rc and RD, respectively. During these times, the microprocessor 27 will generate a signal of MO DO P P of low logic level. In this way, during normal operation, the signal MO DO PP is a low logic control bit and the three-state separators driving the bus 12C are in a state of high output impedance during intervals when the signals of IM PU LSO SCL and IM PU LSO SDA are at a high logical level. In other words, the push-pull mode is turned off when the IMPULSE SCL and the I MPU LSO SDA are in logical "1". The high logic level of the busbar lines is established through the resistors Rc and RD of coupling to positive when the signal MODE PP is at logical "0". That is, the passive positive coupling resistors change the signals in the lines of the bus between the first and second states (high and low logic levels) at a speed determined by the value of the positive and negative coupling resistor. the load capacity of the busbar lines. Figures 5A through 5 illustrate the relative times of the signals selected in the busbar illustrated in Figure 3. Now the silhouettes of the waveforms associated with the push-pull mode, all of them they follow the form of low capacity load indicated by the solid line. Note that the counterphase mode of the main cell device 2 is suspended while the main device 2 is reading the data supplied by the slave cell 4. This is necessary because, in general, the slave devices in the busbar are not expected to have an impulse capacity in counter phase of the busbar. In fact, it should be noted that the recognition interval shown in Figures 2A to 2D is the result of the slave device 4 which releases or maintains the low SDA bus line. When the slave devices return data, the master device must have freed the itk ío line from the SDA busbar so that this line of the busbar can be coupled to negative by a slave device. In addition, the SDA bus bar clock must be delayed during the reading period to allow a slow rise time of the returned data signal in the SDA busbar.

As shown in Figures 5A to 5D, during the recognition interval corresponding to the ninth clock cycle, in which the idled slave device returns a data bit to the master device, the master device is switched from push to normal impulse. It shows that the The period of the clock is arbitrarily increased by a factor of 2 in the recognition interval. The control of the clock period is provided by a software executed by the microprocessor 27. When the slave device is returning either read data or a recognition bit (either a logical or high logic) under the ninth pulse of the clock) the slave device places the data in the busbar when the line of the SDA busbar is coupled to negative or by allowing the line of the SDA busbar to be positively coupled by the bus resistor. coupling to positive. The purpose of increasing the period of the impulse clock in the line of the SCL bus when the slave device is returning data, is to adjust the fact that the slave device is not capable of operating in the push-pull mode. A fully slave device (defined within it as a slave device that does not have the power to act as a master device) never positively couples the busbar with the push-pull mode. However, it should be noted that as another embodiment of the invention, it is possible to implement the control of the busbar through the push-pull mode using a master device acting a slave device. Although the invention has been described in detail herein, with reference to its preferred embodiment, it should be understood that this description is only exemplary and should not be considered with a limiting sense. It should also be understood that many changes in the details of embodiments of the invention and additional embodiments of the invention will be apparent and can be carried out by persons with sufficient skill in the art with reference to this disclosure. For example, although described with respect to a mode incorporating a data bus in accordance with protocol 12C, the invention can be applied to other data bus protocols that incorporate parallel or serial data communication. An example of another protocol for data bus for which the invention can be useful is the I M data bus protocol based on ITT. Also, although conventional slave devices do not have the push-pull operation mode, fully slave devices can be manufactured by the device manufacturers, taking iaccount the invention disclosed herein, which incorporates a three-state separator as well as it is included in the master device as described above. In addition, although signal polarities of logic control and circuit implementations have been described, those skilled in the art will appreciate that the modifications can be made to the structure and function of the invention without departing from the spirit and scope of the invention. same and it is contemplated that all additional changes and embodiments fall within the true spirit and scope of the invention as claimed below.

Claims (10)

1. RETIREMENT D ISCTION IS 1. An apparatus for controlling the transmission of data in a data bus, the apparatus comprises: a passive device coupled to the data bus to establish a first mode of operation during which data signals are transmitted on the bus collector at a first speed; and an active device coupled to the bus bar to establish a second mode of operation during which the signals are transmitted in the bus bar at a second speed, the first speed is different from the second speed.
2. 2. The apparatus according to claim 1, wherein the data bus is a busbar 12C. The apparatus according to claim 2, wherein the passive device has a positive coupling resistor for coupling the busbar to a voltage source and the active device has a counter-phased device coupled between the busbar and the source tensile . 4. The apparatus according to claim 3, wherein the data is transmitted between a master device and a slave device and the counterphase device couples the master device with the data bus. 5. The apparatus according to claim 1, wherein the active device is disabled during the first mode of operation, thereby preventing the shape of the active device from affecting the first speed. The apparatus according to claim 5, wherein the passive device operates during the first and second modes of operation to switch the signal in the bus between high logic and low logic states. The apparatus according to claim 5, wherein the data is transmitted between a master device and a slave device, the push-pull device couples the master device with the bus bar and the first mode of operation corresponds to one of a recognition condition. or to a condition of data reading, during one of which, the slave devices communicate the information to the master device. The apparatus according to claim 7, wherein the data bus is a data bus 12C. 9. A television signal processing system that has an apparatus for controlling the transmission of data in a busbar, the apparatus comprises: a passive device coupled with the busbar to establish a first mode of operation during which, the data signals are transmitted in the bus at a first speed; and an active device coupled to the busbar to establish a second mode of operation, during which the signals are transmitted to the busbar at a second speed, the first speed is different from the second speed, wherein the first The mode of operation occurs during the interval corresponding to the first portion of a television signal representing the video information and the second mode of operation occurs during a corresponding interval to the second portion of the television signal which represents other information. different from the video information. 10. The apparatus according to claim 9, wherein the data bus is a data bus 12C, the data is transmitted between a master device and a slave device, the active device includes a counterphase device which couples the data bus. master device with the data bus, the active device is disabled during the first mode of operation by which it prevents the shape of the active device from affecting the first speed and the first operating mode corresponds to one of a recognition condition or a read condition during which one of the slave devices communicates the information to the master device. 1 1. A method for controlling the data transmission in a data bus comprising the steps of: establishing a first mode of operation during which the data signals are transmitted in the bus at a first speed; and establishing a second mode of operation during which the signals are transmitted in the busbar at a second speed, the first speed is different from the second speed. RESU M IN The information is coupled with a data bus, such as a data bus 12C, using a push-pull circuit. The push-pull circuit is provided for data communication at two different data rates. The push-pull circuit includes a positive coupling device that is enabled during a first push-pull mode to provide a high data rate. During a second normal mode of operation, the active positive coupling device is disabled, providing a low data rate. When the positive coupling device is deactivated, the clock and data buss are driven by the external resistors connected thereto, at a data rate lower than the data rate during the first mode.