CN113113943B

CN113113943B - System and method for dual port communication and power delivery

Info

Publication number: CN113113943B
Application number: CN202110040702.2A
Authority: CN
Inventors: 刘武光; S·默克尔
Original assignee: Maxim Integrated Products Inc
Current assignee: Maxim Integrated Products Inc
Priority date: 2020-01-13
Filing date: 2021-01-13
Publication date: 2024-05-28
Anticipated expiration: 2041-01-13
Also published as: CN113113943A; DE102021100567A1

Abstract

Described herein are embodiments of dual port communication and power delivery for single wire applications. Embodiments of a single wire bridging device for providing a dual port link for two single wire master devices to communicate with each other in a multi-voltage system while intermittently achieving a charging voltage are disclosed. This configuration may be used to set a bi-directional pass-through mode that allows level shifted fast logic signals to pass through between the two single-wire links. The timer may also be configured to timeout the transparent mode based on the inactivity of the edge. Power may be obtained directly for operation from one of these links, eliminating the need for external power supply when local power is not available. Another single-wire link provides local access and pass-through modes when local power is available. This configuration makes the two-contact solution easy to be both a communication channel and a power supply for battery charging.

Description

System and method for dual port communication and power delivery

Cross Reference to Related Applications

The present application is based on the benefits of 35U.S. c. ≡119 (e) claiming that the inventors filed on 1 month 13 2020 are Liu Wuguang and stoke-merck and entitled "SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY [ systems and METHODs FOR DUAL port communications and power delivery ]", provisional application serial No. 62/960,580 and the inventors filed on 23 month 12 2020 are Liu Wuguang and stoke-merck and entitled "SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY [ systems and METHODs FOR DUAL port communications and power delivery ]", which are hereby incorporated by reference in their entireties.

Background

A. Technical field

The present invention relates generally to communications and power delivery and methods of its implementation in single wire applications.

B. Background art

In single-wire applications, the power management unit assists in maintaining communication between the first electronic device and the second electronic device via a single-wire I/O interface. The single-wire I/O interface may be used as an input port, an output port, and/or a power supply port so that the entire I/O interface may be simplified. This configuration is beneficial for various applications, especially for devices with smaller size and which do not require high data rates.

Various efforts have been made to improve communication and power delivery methods for single wire applications. Since a single-wire I/O interface is shared as a data communication channel and a power channel between two electronic devices, the interface needs to be managed to avoid any conflicts in interface usage, especially when both devices are master devices. Furthermore, the first electronic device and the second electronic device may communicate via a single-wire I/O interface in a multi-voltage system, which requires the I/O interface to be adapted for operation.

It would therefore be desirable to have a system for communication and power delivery between electronic devices and a method of implementing the same in a single wire application.

Disclosure of Invention

Embodiments of the present invention relate to communication and power delivery for single wire applications.

In one or more embodiments, the dual port circuit is a slave bridging device that provides two single wire links for two single wire master devices to communicate with each other in a multi-voltage system. Each single wire link shares a buffer for transmitting data. In addition, the dual port circuit may support a bi-directional pass-through mode that allows level shifted fast logic signals (e.g., up to 512 kbps) to pass through between the two single-wire links. The dedicated timer may be configured to timeout the transparent mode based on the inactivity of the edge. When large amounts of data are transferred, this may be configured for UART-to-UART communication either simplex (only one direction) or half duplex (devices transmitting and receiving in turn). Status bytes can be used to know when the buffer is full and the idle logic state of the two single-wire links. This operation may draw power directly from the single-wire IOA link, eliminating the need for external power supply when local power is not available. The single-wire IOB link provides local access and pass-through modes when local power is available. In one or more embodiments, the margin of the single-wire IOA link is 5V to achieve charger power on the single-wire bus. This may be accomplished by detecting with a comparator that the voltage on the single-wire IOA link is greater than a predetermined voltage (e.g., 4V). The predetermined voltage is typically greater than an operating voltage (e.g., 3.3V) on the single-wire link IOA for data communication.

In one or more embodiments, a single wire bus system is disclosed that includes a dual port circuit as a slave bridge device. The hardware configuration, transaction sequence, and single wire signaling (signal type and timing) of a single wire bus system are described, respectively. One or more single-wire protocols define bus transactions that originate from the falling edge of a synchronization pulse from a bus master based on bus state during a particular time slot. In one or more embodiments, a single wire bus has only a single wire; each device on the bus needs to drive the bus at the appropriate time. To facilitate this, each device attached to the single wire bus may have an open drain output or a tri-state output. In one or more embodiments, the idle state of the single wire bus is set high. In the event that a transaction needs to be suspended, it may be desirable for the bus to remain idle to resume the transaction. If this does not occur and the bus remains low for more than a predetermined time, one or more devices on the bus may be reset.

In one or more embodiments, a protocol for accessing dual port circuits through an IOA or IOB single-wire port is disclosed. These protocols may include initialization, ROM function commands, device function commands, and transactions/data.

Drawings

Reference will now be made to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. The drawings are intended to be illustrative, and not limiting. While the invention is generally described in the context of these embodiments, by doing so is not intended to limit the scope of the invention to the specific features of the embodiments depicted or described.

FIG. 1 depicts a block diagram of a first electronic device in communication with a second electronic device via a single-wire I/O bus.

Fig. 2 depicts an exemplary block diagram of a dual port circuit coupled between two single wire host circuits according to various embodiments of the invention.

Fig. 3 depicts an exemplary block diagram of a dual port circuit coupled in a multi-voltage system in accordance with various embodiments of the invention.

Fig. 4 depicts a simplified block diagram of a dual port circuit in an application where a bluetooth headset communicates with a charging box, according to various embodiments of the invention.

Fig. 5 depicts a detailed block diagram of a dual port circuit in an application where a Truly Wireless Stereo (TWS) headset communicates with a charging box, according to various embodiments of the invention.

Fig. 6A depicts an exemplary schematic of a dual port circuit for a single wire application in accordance with various embodiments of the invention.

Fig. 6B depicts an alternative schematic of a dual port circuit for a single wire application in accordance with various embodiments of the invention.

Fig. 7 depicts an exemplary bitmap of a ROM ID for a dual port circuit in accordance with various embodiments of the present invention.

FIG. 8 depicts a diagram of PIO output timing according to various embodiments of the invention.

FIG. 9 depicts a diagram of read/write timing according to various embodiments of the invention.

Fig. 10 depicts an initialization sequence required to begin communicating with a dual port circuit in accordance with various embodiments of the present invention.

FIG. 11 depicts an exemplary process diagram of a ROM function command stream for a single-wire application, according to various embodiments of the invention.

FIG. 12 depicts a process diagram of a device function command stream for a single-wire application, according to various embodiments of the invention.

Fig. 13 depicts a state diagram of the operation of a dual port circuit according to various embodiments of the invention.

Fig. 14 depicts a noise suppression scheme in accordance with various embodiments of the invention.

Those skilled in the art will recognize that the embodiments and examples of the present invention can be practiced in accordance with the description. All such implementations and embodiments are intended to be included within the scope of the present invention.

Detailed Description

In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without these details. Furthermore, those skilled in the art will appreciate that the embodiments of the invention described below may be implemented in a variety of ways, such as a process, an apparatus, a system, a device, or a method, on a tangible computer-readable medium.

The components or modules shown in the figures illustrate exemplary embodiments of the invention and are intended to avoid obscuring the invention. It should also be understood that throughout this discussion, components may be described as separate functional units that may include sub-units, but those skilled in the art will recognize that various components or portions thereof may be separated into separate components or may be integrated together, including in a single system or component. It should be noted that the functions or operations discussed herein may be implemented as components. The components may be implemented in software, hardware, or a combination thereof.

Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, the data between these components may be modified, reformatted, or otherwise changed by intermediate components. Moreover, additional connections or fewer connections may be used. It should also be noted that the terms "coupled", "connected" or "communicatively coupled" (communicatively coupled) should be understood to include direct connection, indirect connection through one or more intermediate devices, and wireless connection.

In this specification, reference to "one embodiment," "preferred embodiment (PREFERRED EMBODIMENT)", "an embodiment (an embodiment)", or "embodiments (embodiments)" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention and may be included in more than one embodiment. Moreover, appearances of the phrases in various places throughout this specification are not necessarily all referring to the same embodiment or embodiments.

Certain terminology is used in the various places throughout this specification for the purpose of description and should not be taken as limiting. The service, function, or resource is not limited to a single service, function, or resource; the use of these terms may refer to a set of related services, functions, or resources that may be distributed or aggregated. The terms "include", "comprising", "including", and "including" are to be construed as open-ended terms and any list below is exemplary and not intended to be limited to the listed items.

Furthermore, those skilled in the art will recognize that: (1) certain steps may optionally be performed; (2) steps may not be limited to the particular order set forth herein; (3) certain steps may be performed in a different order; and (4) some steps may be accomplished simultaneously.

Fig. 1 depicts a block diagram of a first electronic device 110 in communication with a second electronic device 120 via a single-wire I/O bus 115. In one or more embodiments, the first electronic device 110 acts as a master device and the second electronic device 120 acts as a slave device. The single wire bus 115 may have only a single wire. It is therefore important that each device on the bus drives the bus at the appropriate time. In one or more embodiments, to facilitate this, each device attached to the single wire bus has an open drain output or tri-state output. In one or more embodiments, the idle state of the single wire bus is set high. In the event that a transaction needs to be suspended for any reason, the bus is required to remain idle if the transaction is to be resumed. If this does not occur and the bus remains low for more than a certain time, e.g. 15.5 mus (overdrive speed), one or more devices on the bus will be reset. Although the name "single line", all devices may have a second line, a ground connection for permitting current to flow back through the data line. Communication occurs when the master or slave briefly pulls the bus down from V _PUP, i.e., grounds the pull-up resistor (R _PUP) through its output MOSFET.

In some cases, single-wire communication may be implemented between a master device and a slave device, where the master device initiates activity on the bus, thereby simplifying the process of avoiding collisions on the bus. The protocol may be built into the software of the master device to detect conflicts. After the collision occurs, the master device may retry the communication. When two single-wire master devices desire to communicate with each other, a single-wire slave bridge device or circuit may be required to establish a link between the two single-wire master devices. Fig. 2 depicts an exemplary block diagram of a dual port circuit 230 coupled between two single-wire host devices or circuits 210 and 220, according to various embodiments of the invention. In one or more embodiments, dual port circuit 230 is a slave bridge device that includes a first single-wire input/output port (hereinafter IOA) 231 and a second single-wire input/output port (hereinafter IOB) 232 that communicate with host circuits 210 and 220 via IOA link 233 and IOB link 234, respectively. Dual port circuit 230 may further include additional general purpose input/output ports (PIOA, PIOB, or PIOC as shown in fig. 2). The IOA port may be used to harvest V _DD power during the idle high time of IOA link 233 and store energy in an internal parasitic capacitor. In one or more embodiments, IOA link 233 and IOB link 234 may include a diode instead of a resistor for each link, where the anode side of the diode is coupled to dual port circuit 230.

In one or more embodiments, to coordinate communication between the two single-wire input/output ports, dual-port circuit 230 further includes a token pin 235 configured to indicate which single-wire input/output port obtained the communication token. When the token pin is set to a first logic level (e.g., logic low), the IOA link is set for single-wire communication; and when the token pin is set to a second logic level (e.g., logic high) opposite the first logic level, the IOB link is set for single-wire communication. In one or more embodiments, the token pin 235 may output a low frequency clock (TOK _F) when the dual port circuit 230 is operating in a pass-through mode that allows level shifted fast logic signals (e.g., up to 512 kbps) to pass through between the two single-wire links. The dedicated timer may also be configured to timeout the transparent mode based on edge inactivity. This may be useful for UART-to-UART communications that are simplex (only one direction) or half duplex (devices take turns transmitting and receiving) when large amounts of data are communicated.

In one or more embodiments, dual port circuit 230 may further include a power receiving port 236 that may be coupled to receive a voltage V _L.V_L for powering the power requirements of the internal digital circuitry and IOA/IOB pins in a pass-through mode, which may be in the range of 1.71V to 5.25V.

In one or more embodiments, dual port circuit 230 may further include a Charger Disable (CD) port that may also function as a general purpose input/output port (e.g., sharing the CD port with the PIOC port, as shown in fig. 2). The CD port may be floating (i.e., non-conductive) when IOA port 231 is nominally below a threshold voltage (e.g., 4V). Otherwise, when the IOA is above 4V, the CD port will be actively low due to turning on the controllable switch 237 (e.g., P-type transistor, N-channel transistor, P-channel transistor, etc.), thereby enabling the charger 240. The PMOS transistors depicted in the drawings are for purposes of illustrating the application and are not limiting of the choice of switches. Those skilled in the art will appreciate that other types of switches (e.g., N-type, N-channel, P-type, P-channel, BJT switches) may also be suitable for use in one or more embodiments of the present application.

In one or more embodiments, the dual port bridge circuit may be applied for single line communication in a multi-voltage system. Fig. 3 depicts an exemplary block diagram of a dual port circuit coupled in a multi-voltage system including a first device 310 and a second device 320, in accordance with various embodiments of the present invention. The first device 310 includes a first Microcontroller (MCU) 312 operating at 3.3V, and the second device 320 includes a second Microcontroller (MCU) 322 operating at 1.8V. A dual port circuit 324 integrated within the second device 320 is coupled between the first MCU and the second MCU. Dual port circuit 324 includes a first single-wire port IOA in communication with first MCU312 via a first single-wire bus 325 and a second single-wire port IOB in communication with second MCU 322 via a second single-wire bus 326. Through the dual port circuit 324, the first device 310 (or the first MCU 312) and the second device 320 (or the second MCU 322) may communicate in a single line even though they operate at different voltages.

Fig. 4 is an exemplary block diagram 400 of a dual port circuit in an application where a bluetooth headset 420 communicates with a charging box 410 in accordance with various embodiments of the present invention. The charging box 410 includes a first Microcontroller (MCU) 412 for charging and I/O control. Bluetooth headset 420 includes a circuit (e.g., a bluetooth audio chip) 422 and a dual port circuit 424. Dual port circuit 424 includes a first single-wire port IOA in communication with first MCU412 via a first single-wire bus 425 and a second single-wire port IOB in communication with circuit 422 via a second single-wire bus 426. The first single wire bus 425 may serve as a communication channel for data exchange or as a charging path. The first MCU412 has an enable port (EN) coupled to control a controllable switch 414 switchably coupling the first single wire bus 425 to a 5V voltage source for charging the bluetooth headset 420. Once the voltage of the first single-wire bus 425 increases to 5V, the Charger Disable (CD) port in the dual port circuit 424 is pulled low to turn on the controllable switch 430 (e.g., PMOS switch) to engage the 5V voltage source to the battery charger 440 to activate battery charging. When the first single wire bus 425 serves as a communication channel for data exchange, the first single wire bus 425 is decoupled from the 5V voltage source by opening the controllable switch 414 and is operably coupled to the 3.3V voltage source for data communication between the GPIO port of the first MCU412 and the single wire I/O port (IOA) of the dual port circuit 424.

Similar to the dual port circuit 230 shown in fig. 2, the dual port circuit 424 also has a second single wire input/output port (IOB) that communicates with a bluetooth audio chip 422 via IOB link 426 that is operatively coupled to a 1.8V voltage source. The dual port circuit 424 may further include additional general purpose input/output ports (PIOA, PIOB, or PIOC) and a token pin (not shown in fig. 4) configured to indicate which single wire input/output port enables communication.

Fig. 5 depicts a detailed block diagram 500 of a dual port circuit in an application where a Truly Wireless Stereo (TWS) headset 520 communicates with a charging box 510, according to various embodiments of the invention. It should be noted that certain blocks depicted (i.e., heart rate, temperature, etc.) may be optional, and that the figures may not be limited to the elements depicted. The communication may support a universal asynchronous receiver/transmitter (UART) pass-through mode between the headset 520 and the charging box 510. The charging box 510 may include a rechargeable battery 515 that provides charging power to the headset 520. The charging box 510 may be powered by an external power source via a USB interface 516, which may also be coupled to the rechargeable battery 515 via an internal battery charger 517 to charge the rechargeable battery 515. The basic layout of block diagram 500 may be similar to block diagram 400 shown in fig. 4. Additionally, in fig. 4, the 5V power supply for powering the single-wire charge/IO link 525 may be from the 5V DC-DC boost circuit 514 for charging purposes. Alternatively, the power supply for powering the single-wire charge/IO link may originate directly from the rechargeable battery 515. The MCU 512 may further include additional GPIO pins for receiving additional information (e.g., charge case cover detection, left headset battery state, right headset battery state, etc.). In one or more embodiments, the charging box 510 shown in fig. 5 has a single wire interface (single wire interface) for communicating with the headphones 520 and the headphones 560 shown in fig. 5. In one or more embodiments, headphones 520 and 560 receive the charging voltage alternately or simultaneously. It will be appreciated by those skilled in the art that the charging box 510 may be modified to have additional single-wire interface(s) to support communication with multiple headsets (e.g., left and right headsets). For example, the charging box 510 may charge a plurality of headphones simultaneously or alternately, and may be in single-wire data communication with the plurality of headphones simultaneously or alternately. Such modifications are intended to fall within the scope of the present invention.

In one or more embodiments, dual port circuit 524 has a first single wire input/output port (IOA) that communicates with charging box 510 via a single wire charge/IO (single wire) link 525. Once the dual port circuit 524 senses that the voltage on the single-wire charge/IO link 525 is above a predetermined threshold (e.g., > 4V), the Charger Disable (CD) port in the dual port circuit 524 is pulled low to turn on the controllable switch 530, thereby engaging a 5V voltage source to the battery charger 540 to charge the battery 550, which may be a lithium ion battery. In one or more embodiments, bluetooth audio chip 522 may communicate with battery charger 540 via an I2C interface to exchange information such as charging current, battery status, and the like. Audio chip 522 may also receive an interrupt request (or IRQ) from battery charger 540 if one or more parameters exceeds a determined threshold. For example, the battery capacity of the internal battery 515 in the charging box 510 (e.g., between 1000mAh and 2000 mAh) may be greater than the battery capacity of the battery (battery 550) in the left earphone, the right earphone, or both (e.g., between 60mAh and 150 mAh).

Dual port circuit 524 also has a second single wire input/output port (IOB) that communicates with bluetooth audio chip 522 via an IOB link. The dual port circuit 524 may further include an additional general purpose input/output port (PIOA, PIOB, or PIOC) and one of the GPIO pins (e.g., PIOA pin shown in fig. 5) may be used for UART communication with the bluetooth audio chip 522 via a GPIO pin (e.g., GPIO 3) in the chip 522.

Fig. 6A is an exemplary schematic diagram of a dual port circuit 600 for a single wire application in accordance with various embodiments of the invention. The dual port circuit 600 has eight ports or pins: a first single wire I/O pin (IOA) 611 for a first single wire (single wire) link, a second single wire I/O pin (IOB) 612 for a second single wire (single wire) link, a ground pin 613, a default Charge (CD) pin 614 (which may also function as a GPIO pin: PIOC), a token pin 615, a first GPIO Pin (PIOA) 616, a second GPIO Pin (PIOB) 617, and a V _L pin 618 for receiving a low power voltage V _L.

Internally, dual port circuit 600 may further include a set of functional commands 620 (which may include single-wire ROM functional commands and device functional commands), a pass-through mode controller 630, a register 640, a voltage regulator 650, and a voltage comparator 660. In one or more embodiments, each single-wire link shares an 8-byte ROMID 622, global configuration bytes, and a data buffer 626 (e.g., an 8-byte buffer) for transferring data, all of which may be accessed by the function command 620. In addition, each single-wire link may further share one status byte, three configurable open-drain GPIO pins. The status bytes, POI information, and configuration bytes may be stored in registers accessible to the function command 620. Voltage regulator 650 may be switchably coupled to low power voltage V _L or voltage V _DD on the IOA link and output a regulated voltage V _REG that is used to power internal circuitry and voltage comparison.

In one or more embodiments, dual port circuit 600 provides an interface to allow: power to charger, dual single wire master communication, GPIO extensions and timer limited logic level transitions are turned on the single wire bus. The integrated comparator 660 may be used to compare the voltage on the IOA link (V _DD) to a predetermined voltage (V _REG) and thus turn on the charger power or single-wire IOA access. In one or more embodiments, a voltage divider is applied to reduce V _DD to a desired voltage level suitable as an input to comparator 660. When desired, dual port circuit 600 may operate the IOA link with an internal parasitic power supply, while the IOB single wire link may operate with a low power supply (V _L). Regardless of the presence or absence of V _L, the parasitic power supply has access to all registers, ROMIDs, and status information. Data buffer 626 is used to exchange data between the two single-wire links, the IOA and the IOB. Three general purpose I/O pins (PIOA/B/C) may provide GPIO extensions to enable additional functionality. The level shift direction may be selected by any single wire link and allows serial logic data to be transferred between the IOA and the IOB at a higher rate (e.g., up to 512 kbps).

Fig. 6B depicts an alternative schematic of a dual port circuit for a single wire application in accordance with various embodiments of the invention. The dual-port circuit 670 is similar to the dual-port circuit 600 shown in fig. 6A, except for some differences. One difference is that in dual port circuit 670, function command 620 outputs PTM signal 672. When PTM signal 672 is high, a pass-through device (e.g., nMOS switch 674) is turned on to allow bi-directional UART communication between the IOA and IOB via link 676. The IOA high-side to IOB low-side level transition may be achieved by limiting the gate of nMOS 674 to the low-side V _L supply. In one or more embodiments, in the pass-through mode, IOA pull-up voltage V _PUPA may need to be greater than or equal to V _L. Further, in dual port circuit 670, IOA pin 611 and IOB pin 612 may be coupled to function command 620 via buffer 681 and buffer 682, respectively, wherein the outputs of the two buffers are coupled to function command 620. Further, in dual port circuit 670, token pin 615 is coupled to function command 620 via token pin buffer 683 and token pin nMOS 684, wherein an input of token pin buffer 683 is connected to function command 620.

Token operation

In one or more embodiments, the dual port circuit detects the voltage on the IOA/IOB links and automatically switches the communication token between these links. Selection of the IOA link or IOB link is controlled by token pin 615. The pin indicates which single wire side obtained the communication token. In one or more embodiments, a logic low at the token pin represents the IOA side and a logic high represents the IOB side. In one or more embodiments, the token pin 615 outputs a low frequency clock (TOK _F) when in pass-through mode. In addition, impedance checking may be accomplished by software, as appropriate.

In one or more embodiments, each single line link shares an 8-byte buffer for transferring data. Also, the two single-wire links share an 8-byte ROMID, a global configuration byte, a status byte, and three configurable open drain GPIO pins. Each ROMID is a unique 64-bit registration number that has been programmed into the device at the time of shipment. The configuration byte may be used to set a bi-directional pass-through mode that allows level shifted fast logic signals up to 512kbps to pass through between the two single-wire links. The status byte can be used to know when the buffer is full and the idle logic state of the two single-wire links. Power is taken for operation directly from the single-wire IOA link, eliminating the need for external power supply when local power is not available. The single-wire IOB link provides local access and pass-through modes when local power is available.

In one or more embodiments, dual port circuit 600 contains a unique ROM ID that is 64 bits long. The ROM ID may provide tracking capabilities for the dual port circuit. The first 8 bits are a single-line family code. The next 48 bits are the unique serial number. As shown in fig. 7, the last 8 bits are the Cyclic Redundancy Check (CRC) of the first 56 bits. In one or more embodiments, a single-line CRC is generated using a polynomial generator consisting of a shift register and XOR gates. The polynomial may be denoted as X ⁸+X⁵+X⁴ +1.

Table 1 summarizes a number of device function commands. Within the device function command flow diagram (shown in FIG. 13), data transfer is verified by a multi-bit type Cyclic Redundancy Check (CRC) (e.g., CRC-16) 624 when writing and reading are performed.

TABLE 1 overview of device function commands

Command	Description of the invention	Type(s)
			Write configuration	Universal configuration	Global situation
Reading configuration	Universal configuration	Global situation
			Write buffer	Write buffer	Memory device
Read buffer	Read buffer	Memory device
			Reading status	Reading status	Universal use
PIO write	PIO write turn-on or floating	Access to
			PIO read	PIO reads logic states	Access to
Write start value	Writing to a start value register	Universal use
			Reading the start value	Reading a start value register	Universal use

In one or more embodiments, the write configuration command is used to set the configuration registers. The write configuration sets the global configuration of the device. The SEL bit may be used for pin mode selection between CDs and PIOC. The default value is a comparator function for detecting a condition in which a charge supply is detected on the IOA pin or in which the IOA is a single wire link. In addition, level shifted transparent mode (PTM bit) may be used when simplex or half duplex UART communication between the IOA pin and the IOB pin is desired. The level shifter may communicate up to 512kbps until the timer expires the pass-through mode when the IOA/IOB pin is inactive. If activity on the IOA/IOB bus is detected, the timer is reset again to the value set in the start value register (SVAL bits) to maintain the connection. In normal single-wire operation, some applications may require interrupt support for the case where the buffer has been written. This is accomplished by providing PIOA/B with a BUFA/B flag output with inverse logic. Thus, if the BUFA/B flag is set to '1', then the PIOA/B pin will conduct. If the BUFA/B flag is not set, then PIOA/B pins will not conduct. In one or more embodiments, some restrictions (e.g., requiring the presence of VL power in pass-through mode) may be applied to the write configuration command.

TABLE 2 writing configuration parameter bytes

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

PULLUP

QM

PTM

BUFBPE

BUFAPE

SEL

Table 2 shows the parameter bits of the write configuration command, and table 3 shows the sequence of the write configuration. The details of some of the parameter bits are as follows.

Bit 0 Select (SEL). The PIOC pin function is operable when set to 1. When set to 0 (default), the CD pin function is operable.

Bit 1 BUFA port Enable (BUFAPE). When set to 1, the PIOA pin will output the inverse of the BUFA flag in the status register. When set to 0 (default), the PIOA pin will be normally accessed.

Bit 2 BUFB port enabled (BUFBPE). When set to 1, the PIOB pin will output the inverse of the BUFB flag in the status register. When set to 0 (default), the PIOB pin will be normally accessed.

Bit 3-clear mode (PTM). When set to 1, PTM is enabled and the timer begins monitoring the activity of the IOA/IOB pin (i.e., falling edge transition) and outputting a clock on the token pin. The timer will reset the activity to the start value for any falling edge to maintain the PTM. If no activity occurs, the PTM will automatically return to the normal single line operating state and the PTM bit will return to 0 when the timer expires. When set to 0 (default), pass-through mode is disabled and a timer is used to monitor whether the IOA pin transitions to and maintains the "logic low" state of the IOA pin. The falling edge of the IOA will set the timer to its starting time value. If the timer expires and it is confirmed that a logic low still exists, a token is passed to the IOB link (i.e., no other falling edge transition occurs). When the IOB link has a token, the timer will continue to repeat and test whether the IOA link state remains "logic low". However, if another falling edge transition occurs before the timer expires, the "logic state" will exit to the appropriate state (e.g., the IOA link state "idle logic high") when the timer expires. For more details about the state, see the TWS truth table.

Bit 4 Quiet Mode (QM). When set to 1, QM is enabled and the timer begins to monitor the activity of the IOA pin (i.e., falling edge transition) and output a logic high on the token pin. The timer will be reset to a start value for any IOA pin falling edge activity to maintain QM. If no other falling edge IOA activity occurs, the QM will automatically return to the normal single-wire operating state, and when the timer expires the QM bit will return to 0.

Bit 5 pull up (PULLUP). In one or more embodiments, when set to 1, a pull-up resistor of 5M is connected from the IOA link to the VL. When set to 0 (default), the pull-up resistor is disconnected from VL and the same resistor becomes a pull-down resistor to ground. In this way, the IOA pin will not hang when no device is connected and a single-wire IOB link will be accessed.

TABLE 3 write configuration sequence

In one or more embodiments, a read configuration command is used to read the configuration registers to confirm the settings. Tables 4 and 5 show the parameter bits and sequences of the read configuration commands, respectively.

TABLE 4 reading configuration parameter bytes

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

PULLUP

QM

PTM

BUFBPE

BUFAPE

SEL

TABLE 5 reading configuration sequence

The details of the parameter bits of the read configuration command are as follows.

Bit 0 Select (SEL). The bit state is read.

Bit 1 BUFA port Enable (BUFAPE). The bit state is read. Bit 2 BUFB port enabled (BUFBPE). The bit state is read.

Bit 3-clear mode (PTM). The bit state is read.

Bit 4 Quiet Mode (QM). The bit state is read.

Bit 5 pull up (PULLUP). Whether the pull-up resistor is connected (1) or disconnected (0) is read.

In one or more embodiments, the write buffer command is used to write a temporary value to a volatile buffer 626 that is used to transfer bytes to/from a single-wire IOA link or IOB link. In one or more embodiments, if Byte Length (BLEN) >8d, the buffer length is set to 8d. A BLEN of zero may mean that there is no data to load. If the IOA link or the IOB link has tokens, they can only write to the buffer. During operation, a flag of BUFA or BUFB is set in the read status register.

TABLE 6 write buffer parameter bytes

Table 6 shows the parameter bits of the write buffer command and table 7 shows the sequence of the write buffer. In one or more embodiments, the BLEN is in the range of 1 to a maximum length of 8.

TABLE 7 write buffer sequence

In one or more embodiments, the read buffer command is used to read the buffer from a single-wire IOA link or IOB link. In one or more embodiments, if the Byte Length (BLEN) >8d, the value read will be 8d. A zero BLEN may not return any data. In one or more embodiments, the read buffer length bytes are similar to the write buffer parameter bytes shown in table 6, where the BLEN indicates the number of bytes to read.

Table 8 shows the sequence of writing to the buffer. In one or more embodiments, the BLEN is in the range of 1 to a maximum length of 8.

TABLE 8 read buffer sequence

The read status command reads whether the buffer has also been written to, and the logic states of the single-wire IOA link and IOB link. The command is for receiving status information. A means is provided to know whether the IOA link should read the buffer or the IOB link should read the buffer. And also to check the logic state of the IOA/IOB link and whether the comparator has detected a charging voltage on the IOA link. The BUFB and BUFA flags are cleared when the buffer is read. Tables 9 and 10 show the status bytes and the sequence of the read status command, respectively.

TABLE 9 status byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

TRST

TOKS

CMPS

IOBS

IOAS

BUFB

BUFA

Bit 0 buffer flag a (BUFA). Indicating that the buffer is written from the IOA link.

Bit 1 buffer flag B (BUFB). Indicating that the buffer is written from the IOB link.

Bit 2 IOA state (IOAS). Logic state of IOA pin.

Bit 3 iob state (IOBS). The IOB pin AND the VL pin are taken as the logic states of the AND (AND) gates.

Bit 4 comparator state (CMPS). The output state of the comparator. This state may be used to detect a charging voltage when 1 on the IOA pin and indicate no charging voltage when 0 on the IOA pin.

Bit 5 token state (TOKS). The logic state of the token pin. The switching is performed under PTM.

Bit 6 Timer Reset (TRST). In the "logic low" state, this indicates that the timer has restarted with a start value.

TABLE 10 read status sequence

In one or more embodiments, the PIO write command sets the directional drain open PIO pin to a high impedance state that is conductive or non-conductive. To turn on the output transistor, the corresponding bit value is 0. To turn off the output transistor (non-conducting), the bit is set to 1. In this way, the bits transmitted as the new PIO output state arrive at the PIO pin in their true form. In one or more embodiments, an actual PIO to new state transition may occur after a delay of t _REH+t_P from the rising edge of the MS bit of the anti-PIO byte, as shown in fig. 8.

In one or more embodiments, to protect the transmission from data errors, the master device or circuit sets the upper nibble in the PIO output byte to the two's complement to the lower nibble. When the transmission is error free, the PIO state will change. During a PIO write operation, the dual port circuit sets the PIO output state. If the CD pin is set in the configuration register, then PIOCS bits will be invalidated.

Tables 11 and 12 show PIO output bytes and PIO write sequences, respectively.

Table 11.Pio output bytes

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

PIOCS

PIOBS

PIOAS

0

PIOCS

PIOBS

PIOAS

Bit 0 PIOA output state (PIOAS). Setting the bit to 0 (logic low) indicates conduction, or setting the bit to 1 indicates non-conduction (high impedance or logic high by external pull-up).

Bit 1 piob output state (PIOBS). Setting the bit to 0 (logic low) indicates conduction, or setting the bit to 1 indicates non-conduction (high impedance or logic high by external pull-up).

Bit 2 PIOC output state (PIOCS). Setting the bit to 0 (logic low) indicates conduction, or setting the bit to 1 indicates non-conduction (high impedance or logic high by external pull-up).

TABLE 12 PIO write sequence

In one or more embodiments, the PIO read command reads the input logic state of the PIO pin. To protect the transmission from data errors, the master expects the upper nibble in the PIO input byte to be a two's complement to the lower nibble. If the CD pin is set in the configuration register, then PIOCL bits will represent the logic level.

Tables 13 and 14 show the PIO input bytes and PIO read sequences, respectively.

Table 13.Pio input bytes

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

PIOCL

PIOBL

PIOAL

0

PIOCL

PIOBL

PIOAL

Bit 0: pioa level (PIOAL). The logic state of PIOA pins is provided.

Bit 1: piob level (PIONL). The logic state of PIOB pins is provided.

Bit 0: PIOC level (PIOCL). The logic state of PIOC pins is provided.

TABLE 14 PIO read sequence

In one or more embodiments, the write start value command is used to set the start value of the timer to be reduced. The timer will use this value when it is first started or needs to be repeated.

Tables 15 and 16 show the write configuration parameter bytes and the write timeout value sequence, respectively.

TABLE 15 writing configuration parameter bytes

Bits 7:0: timeout Value (TVAL). The end time value of the timer is set. In one or more embodiments, the timer timeout value may be expressed as duration = TVAL x 2ms. For example, for TVAL bits of 8, the maximum timer duration is set to 512ms.

TABLE 16 write timeout value sequence

In one or more embodiments, a read timeout value command is used to read the timeout value register to confirm the setting. The read configuration parameter bytes may be similar to the write configuration parameter bytes shown in table 15. Table 17 shows the read configuration parameter bytes.

TABLE 17 sequence of read timeout values

Embodiments of pass-through operation

In one or more embodiments, in a pass-through mode (enable timer), the dual port circuit 600 may function as an open-drain bi-directional level shifter. This may be accomplished through two inverting gate paths 632 and 634 to provide bi-directional level shifting between the IOA and IOB links with this mode enabled in the configuration register (e.g., by setting the PTM bit to 1). The direction of the pass-through operation may be controlled via a pass-through controller 630 integrated within the dual port circuit 600 to selectively engage one of the desired inverting gate paths 632 or 634 via switches SW1 or SW 2. When the input is logic high, the corresponding drain open N-FET is not conductive. When the input is logic low, the corresponding drain open N-FET is turned on. In one or more embodiments, dual port circuit 600 requires external pull-up resistors from IOA V _DD and IOB V _L, allowing operation with an open drain output. In one or more embodiments, the one or more internal circuitry may assist in the logic state transition of the IOA link by removing internal parasitic capacitances in the PTM.

Power supply description

In one or more embodiments, IOA pin 611 is used to harvest V _DD power during the idle high time of the IOA link and store energy in an internal parasitic capacitor. In pass-through mode, V _L is used to power the power requirements of the internal digital circuitry and IOA/IOB pins. In one or more embodiments, V _L may be in the range of 1.71V to 5.25V.

In one or more embodiments, a single wire bus system is disclosed that includes a dual port circuit as a slave bridge device. The system involves hardware configuration, transaction sequence, and single-wire signaling (signal type and timing) aspects. One or more single-wire protocols define bus transactions that originate from the falling edge of a synchronization pulse from a bus master based on bus state during a particular time slot. In one or more embodiments, a single wire bus has only a single wire; each device on the bus needs to drive the bus at the appropriate time. To facilitate this, each device attached to the single wire bus may have an open drain output or a tri-state output. Both single-wire ports (IOA and IOB) of the dual-port circuit are open-drain, the internal circuit of which is equivalent to fig. 1. In one or more embodiments, the idle state of the single wire bus is set high. In the event that a transaction needs to be suspended, it may be desirable for the bus to remain idle to resume the transaction. If this does not occur and the bus remains low for more than a predetermined time, for example 15.5 mus (overdrive speed), one or more devices on the bus will be reset.

In one or more embodiments, protocols for accessing dual port circuits through an IOA or IOB single-wire port may include initialization, ROM function commands, device function commands, and transactions/data.

Initialization of

In one or more embodiments, transactions on a single wire bus begin with an initialization sequence. The initialization sequence may consist of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave. The presence of a pulse lets the bus master know that the dual port circuit is on the bus and ready to operate.

Single-wire signaling and timing

To ensure data integrity, dual port circuits may require strict protocols that may consist of four types of signaling on one line: a reset sequence with reset pulses and presence pulses, write-zero (write-zero), write-one (write-one), and read data. In one or more embodiments, the bus master initiates all falling edges except for the presence of a pulse. When not in the transparent mode, the dual port circuit may communicate at overdrive speeds.

In one or more embodiments, to change from the idle state to the active state, the voltage on the single line needs to drop from V _PUP below the threshold V _TL. To go from active to idle, the voltage needs to rise from V _ILMAX beyond the threshold V _TH. The time taken for this rise in voltage can be represented in fig. 9 as epsilon and its duration depends on the pull-up resistor (R _PUP) used and the capacitance of the attached single-wire network. When the logic level is determined without triggering any event, the voltage V _ILMAX is related to the dual port circuit.

Fig. 10 shows an initialization sequence to begin communication with a dual port circuit. Given the correct ROM and device function commands, a reset pulse is followed by a present pulse indicating that the dual port circuit is ready to receive data. If the bus master uses slew rate control for the falling edge, then the line may need to be pulled down for a time of t _RSTL+t_F to compensate for the edge. In one or more embodiments, t _RSTL does not exceed 80 μs.

In one or more embodiments, the bus master enters a receive mode after releasing the line. The single wire bus is pulled to V _PUP through a pull-up resistor or, in the case of a special driver chip, through active circuitry. In one or more embodiments, the single wire bus is pulled to V _PUP through a pull-up resistor. When threshold V _TH is crossed, the dual port circuit waits and then transmits the presence pulse by pulling down the line. To detect the presence of a pulse, the master needs to test the logic state of the single wire line at t _MSP.

In one or more embodiments, immediately after expiration of t _RSTH, the dual port circuit is ready for data communication. In a mixed population network, t _RSTH may need to be extended to a minimum of 48 μs at overdrive speed to accommodate other single-wire circuits or devices.

Read/write time slots

In one or more embodiments, data communication with the dual port circuit occurs in time slots, each of which carries one bit. The write slot transmits data from the bus master to the slave. In the read slot, data is transmitted from the slave device to the master device. Fig. 9 shows the definition of the write slot and the read slot.

In one or more embodiments, the communication begins with the master pulling the data line low. When the voltage on the single line drops below the threshold V _TL, the dual port circuit starts its internal timing generator, which determines when the data line is sampled during the write slot and how long the data is valid during the read slot.

Master to slave

In one or more embodiments, for a write time slot, the voltage on the data line needs to cross threshold V _TH before a write low time t _W1LMAX expires. For a write zero time slot, the voltage on the data line needs to remain below the threshold V _TH until the write zero low time t _W0LMIN expires. In order to obtain the most reliable communication, the voltage on the data line should not exceed V _ILMAX during the whole t _W0L or t _W1L window. After threshold V _TH has been crossed, the dual port circuit requires a recovery time t _REC to prepare for the next time slot.

Slave to master

In one or more embodiments, the read data slot begins as a write slot. The voltage on the data line remains below V _TL until the read low time t _RL expires. During the t _RL window, when the response is 0, the dual port circuit begins to pull the data line low; its internal timing generator determines when the pull-down time has ended and the voltage begins to rise again. When the response is 1, the dual port circuit will not hold the data line low at all and once t _RL ends, the voltage starts to rise.

In one or more embodiments, the sum of t _RL +δ (rise time) on one side and the internal timing generator of the dual-port circuit on the other side defines a master sampling window (t _MSRMIN to t _MSRMAX) in which the master performs a read from the data line. In one or more embodiments, t _RL may need to be as short as possible in order to obtain the most reliable communication, and the master may need to read close to but no later than t _MSRMAX. After reading from the data line, the master waits until t _SLOT expires. This ensures that the dual port circuit has sufficient recovery time t _REC to prepare for the next slot. It should be noted that t _REC specified herein applies only to a single dual port circuit attached to a single wire line. For multi-device configurations, an extension t _REC may be required to accommodate additional single-wire circuits or device input capacitances. Alternatively, an interface may be used that performs active pull-up during a single-wire recovery time, such as a special single-wire line driver.

Single-wire ROM command

In one or more embodiments, once a bus master detects the presence, the bus master may issue one or more ROM function commands supported by the dual port circuit. In one or more embodiments, the ROM function command is 8 bits long. FIG. 11 illustrates an exemplary ROM function flow process in accordance with one or more embodiments of the invention. The process includes determining to issue a read ROM command 1102, determining to issue a match ROM command 1104, determining to issue a search ROM command 1106, determining to issue a skip ROM command 1108, and determining to issue a resume command 1110. A descriptive list of these ROM function commands in fig. 11 is presented in the following section and summarized in table 18 shown below.

TABLE 18 Single-wire ROM Command overview

ROM function commands	Description of the invention
		Searching ROM	Search device
Read ROM	Reading ROM from a device (Single-point branching)
		Matching ROM	Through ROM number selecting device
Skipping ROM	Selecting devices on a single line only
		Recovery	Selecting devices by RC bit setting
Overdrive skip ROM	Putting all devices in overdrive
		Overdrive matching ROM	Putting a device having the ROM in an overdrive state

Search ROM: the bus master may not know the number of devices on the single wire bus or the ROM ID numbers of these devices when the system is initially started. By utilizing the wire-AND (wire-AND) characteristic of the bus, the master can identify the IDs of all slaves using an exclusion procedure. For each bit in the ID number, the bus master issues a triplet slot starting with the least significant bit. On the first slot, each slave device participating in the search outputs the true value of its ID number bit. On the second slot, each slave device participating in the search outputs the complement value of its ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slaves that do not match the bits written by the master stop participating in the search. If both read bits are zero, the master knows that there is a slave from both bit states. By selecting the state to write, the bus master will form a branch in the search tree. After a complete round, the bus master knows the ROM ID number of the individual device. Other rounds identify the ID numbers of the remaining devices.

Read ROM: the read ROM command allows the bus master to read ROM information (e.g., an 8-bit family code), a unique 48-bit serial number, and an 8-bit CRC from ROM integrated within the dual port circuit. This command can only be used when there is a single slave on the bus. If there is more than one slave device on the bus, a data collision (open drain produces a line and result) occurs when all slave devices attempt to transmit simultaneously. The resulting family code and 48-bit serial number result in a CRC mismatch.

Matching ROM: the matching ROM command followed by a 64-bit ROM sequence allows the bus master to address specific dual port circuits on the multi-drop bus. Only a dual port circuit that exactly matches the 64-bit ROM sequence will respond to subsequent device function commands. All other slaves wait for a reset pulse. The command may be used in the case where there is a single device or multiple devices on the bus.

Skip ROM: by allowing the bus master to access device functions without providing a 64-bit ROM ID, the command may save time for a single drop bus system. If there is more than one slave device on the bus and a read command is issued, for example after a ROM command is skipped, a data collision (open drain pull down produces a line and result) on the bus occurs when multiple slave devices are transmitting simultaneously.

And (5) recovering: to maximize data throughput in a multi-drop environment, a resume command may be used. This command checks the state of the RC bit and, in the case that the RC bit has been set, it transfers control directly to the device function command, similar to the skip ROM command. One way to set the RC bit is by successfully executing a match ROM, search ROM, or overdrive match ROM command. Once the RC bit has been set, the device may be repeatedly accessed by a resume command. Another device on the access bus will clear the RC bit, thereby preventing two or more devices from responding to the resume command at the same time.

Device function commands

After a single-wire reset/present loop and a ROM function command sequence is successfully executed, the device function command may be accepted. FIG. 13 depicts a process diagram of a device function command stream for a single-wire application, according to various embodiments of the invention. Following the summary in table 1 shown above, a descriptive list of these device function commands in fig. 13 is presented in the subsequent section.

FIG. 13 is a process diagram of a device function command stream for a single wire application in accordance with various embodiments of the invention. The process begins with a ROM function flow diagram that may be described in fig. 11. At step 1202, a master device (device or circuit) transmits a device function command. At step 1204, write command byte verification is checked. In response to a positive verification (Y), the process proceeds to step 1206, where the master device transmits one or more parameter/data bytes. Subsequently, at step 1208, the master receives CRC-16 (command and parameter/data negation).

In response to a negative verification (N) of step 1204, the process proceeds to step 1210, where the read command byte verification is checked. In response to a positive verification (Y) of step 1210, the process proceeds to step 1212, where the master device receives one or more data bytes. Subsequently, at step 1214, the master receives CRC-16 (command and data negation).

In response to a negative verification (N) of step 1210, or after step 1208 or step 1214, the process proceeds to step 1216, where it is checked whether the master device transmits a reset. If the master transmit reset is no, the process proceeds to step 1218 where the master receives one or more "1 s" and then returns to step 1216 to again perform the master transmit reset check. If the master device transmit reset is yes, the process proceeds to the ROM function flowchart in step 1220.

State diagram

In view of the foregoing description, a state diagram illustrating operation of a dual port circuit in accordance with one or more embodiments of the present invention is shown in fig. 13. The state diagram begins with a power-on reset (POR). At step 1302, it is verified whether there is a charge provisioning on the IOA link. Verification may be implemented by comparing whether the voltage on the IOA link is greater than a threshold voltage V _CMP (e.g., 4V). In response, the process proceeds to step 1304 where the IOA link is set to "state of charge" and the IOB link is set to single line operation (by setting the token pin to high "1" and the CD pin to low "0") and then returns to step 1302 to verify again.

In response to no charge provisioning on the IOA link, the process proceeds to step 1306 where it is verified whether the QM bit is set. If so, the process proceeds to step 1322 where the IOA link is set to "quiet mode" and the QM bit is set to 1 and the timer begins monitoring the activity of the IOA pin and the IOB link is set to single-wire operation (by setting the token pin high and the CD pin high). After step 1322, the process proceeds to single wire communication over the IOA link during which it is verified in step 1328 whether a falling edge occurs before the timer expires. In response to expiration of the timer before another IOA falling edge is received, the process proceeds to step 1334 where the QM bit is cleared and then returns to step 1302. In response to the occurrence of the IOA falling edge before the timer expires, the process proceeds to a timer reset and then returns to step 1322.

If no in step 1306, the process proceeds to step 1308 where it is verified whether the clear mode (PTM) bit is set. If so, the process proceeds to step 1324 where the IOA/IOB link is set to "pass-through mode" where the token pin outputs a clock and the CD pin is set high. Following step 1324, the process proceeds to pass-through communication over the IOA/IOB link during which it is verified in step 1330 whether a falling edge occurs before the pass-through mode timer expires. In response to expiration of the timer before receipt of the other IOA or IOB falling edge, the process proceeds to step 1336 where the PTM bit is cleared and then returns to step 1302. In response to the occurrence of the IOA or IOB falling edge before the timer expires, the process proceeds to a timer reset and then returns to step 1324.

If no in step 1308, the process proceeds to step 1310 where it is verified whether the pull-up bit is set. If so, the process starts a timer and proceeds to step 1326 where the IOA link is set to "impedance check state" via pull-up and the IOB link is set to single-wire operation (where the token pin is set to 1 and the CD pin is set to 1). Following step 1326, the process proceeds to single wire communication over the IOB link during which it is verified in step 1332 whether a falling edge occurs before the timer of the IOB single wire communication expires. In response to expiration of the timer before another IOB falling edge is received, the process proceeds to step 1338 where the pull-up is cleared and the pull-down is resumed, and then returns to step 1302. In response to the IOB falling edge occurring before the timer expires, the process proceeds to a timer reset and then returns to step 1326.

If no in step 1310, the process proceeds to step 1312, where it is verified whether the IOA link is at idle logic high. If yes in step 1312, the process proceeds to step 1314 where the IOA link is set to "single-wire operation" (where the token pin is set to 0 and the CD pin is set to 1). If no in step 1312, the process proceeds to step 1315 to verify whether there is a charge provisioning on the IOA link. Verification may be implemented by comparing whether the voltage on the IOA link is greater than a threshold voltage V _CMP (e.g., 4V). In response to yes in step 1315, the process returns to step 1304. In response to no in step 1315, the process proceeds to step 1306. After step 1314, a timer begins at a falling edge on the IOA link. In step 1316, it is verified whether the IOA is logic low for the entire timer period. In response to the IOA being at logic low during the entire timer period in 1316, the process proceeds to step 1318 where the IOB link is set to single line operation and the IOA link is observed (by setting the token pin to 1 and the CD pin to 1), and then returns to step 1320 where it is verified whether the IOA link is at logic high. In response to the IOA not being at logic low during the entire timer period in 1316, the process proceeds to step 1314. In response to the IOA link being at logic high in step 1320, the process returns to the beginning at step 1302. In response to the IOA link not being at logic high in step 1320, the process returns to step 1318 to continue single line operation on the IOB link.

Improved network behavior

In one or more embodiments, in a single wire environment, line termination may occur during transients controlled by the bus master (single wire driver). Thus, single wire networks are susceptible to noise from various sources. Depending on the physical size and topology of the network, the reflections of the endpoints and branch points may overlap or cancel each other to some extent. Such reflections appear as burs or ringing on single-wire communication lines. Noise coupled onto the single line from an external source may also cause signal glitches. During the slot rising edge, the glitch may cause the slave to lose synchronization with the master and thus cause the search ROM command to sink into the dead office or cause the device-specific function command to cease.

To achieve better performance in network applications, dual port circuits use single-wire front ends that are less sensitive to noise. In one or more embodiments, the IOA/IOB single line front end has a hysteresis and rising edge deferral delay. Fig. 14 depicts a noise suppression scheme in accordance with various embodiments of the invention.

At the transition from low to high, if the line rises above V _TH but does not fall below V _TL, then the glitch is filtered out, as shown by line 1402 in the figure. As shown by line 1404, the rising edge deferred delay (nominal 100 ns) t _REH filters out burrs below V _TL before t _REH expires. In practice, the device does not see an initial rise, but resets t _REH to delay when the line falls below V _TL. If the line is below V _TL after expiration of t _REH, then the glitch is not filtered out, but is instead considered the beginning of the new slot, as shown by line 1406.

In one or more embodiments, there is a falling edge of the pulse with a controlled slew rate, independent of the time slot, to reduce ringing. The drop delay may be specified by t _FPD.

Embodiments of the present invention may be implemented in a variety of applications including, but not limited to, TWS headphones and charger cases, communication bridging between two hosts, dual control general purpose input/output ports, low voltage single rail level translation with tracking ID, and charger power on single line bus use cases, among others. Benefits of this implementation may include: enabling the advanced TWS feature while maintaining the two-contact solution; detecting whether the earphone is inserted into the charger box; power can be obtained from a single-wire IOA link; powering up the present pulse detection when the state of charge is disabled and a 64 bit identification number (ROM ID) is available for reading at the time of insertion; the earphone may detect battery depletion in the charger box; there are available GPIO pins in the accessory for optional features; state information can be transferred between the charging box and the earphone; the pass-through mode is used to quickly update firmware between hosts at a rate of up to 512 kbps; the charger detection pin indicator with the voltage of 5V on the single-wire IOA pin realizes the switchable charger power; the minimal dual single-wire interface reduces cost and interface complexity; capable of operating in a multi-voltage system; communicating with the dual host via two digital signals each at a rate of 90 kbps; the single-wire IOA pin has high ESD resistance; etc.

In one or more embodiments, with respect to power-on presence pulse detection, a power-on presence function may be maintained by detecting whether charging power is present on a first single-wire link (IOA). If charging power is applied to the IOA, a device integrated with the dual port single wire circuit (e.g., a headset) may skip its power-on presence; otherwise, the device will generate a power-on presence when placed in the charging box.

It will be appreciated by those skilled in the art that the foregoing examples and embodiments are exemplary and not limiting to the scope of the present disclosure. It is intended that all permutations, enhancements, equivalents, combinations and modifications thereof that are apparent to those skilled in the art upon a reading of the present specification and a study of the drawings are included within the true spirit and scope of the present disclosure. It should also be noted that the elements of any claim may be arranged in a different manner, including having a variety of dependencies, configurations, and combinations.

Claims

1. A dual port circuit for single wire communication, the dual port circuit comprising:

A first interface for communicating with a first circuit via a first single-wire link, enabling a charging activity using a voltage on the first single-wire link in response to the voltage on the first single-wire link being above a predetermined threshold voltage;

A second interface for communicating with a second circuit via a second single-wire link, one of the first single-wire link and the second single-wire link being enabled for single-wire data communication at a given time, the first interface and the second interface establishing a bi-directional level transition between the first single-wire link and the second single-wire link in a pass-through mode upon activation; and

A buffer in communication with the first single-wire link and the second single-wire link, the buffer for transmitting data during single-wire data communications.

2. The dual port circuit of claim 1, wherein in the pass-through mode, communication between the first interface and the second interface supports simplex or half duplex universal asynchronous receiver/transmitter (UART) communication.

3. The dual port circuit of claim 1, wherein the pass-through mode is timer-enabled.

4. The dual port circuit of claim 1, wherein the charging activity comprises coupling a voltage source to a battery charger configured to charge at least one battery.

5. A method for bridging single-wire communications, the method comprising:

Coupling a first interface of the dual port circuit to the first circuit via a first single wire link;

Coupling a second interface of the dual-port circuit to a second circuit via a second single-wire link;

coordinating operation of the first single-wire link and the second single-wire link by enabling one of the first single-wire link and the second single-wire link for single-wire data communication at a given time, a buffer in communication with the first single-wire link and the second single-wire link and configured to transmit data during single-wire data communication; and

Upon activation, a bi-directional level transition between the first single-wire link and the second single-wire link is established in a transparent mode.

6. The method of claim 5, wherein in the pass-through mode, communication between the first interface and the second interface supports simplex or half duplex universal asynchronous receiver/transmitter (UART) communication.

7. The method of claim 6, wherein enabling the first single-wire link or the second single-wire link for single-wire data communication is controlled by a token pin, the first single-wire link being set for single-wire communication when the token pin is set to a first logic level, the second single-wire link being set for single-wire communication when the token pin is set to a second logic level opposite the first logic level.

8. A system for single-wire communication, the system comprising:

A first circuit including a first input/output interface for communicating via a first single-wire link, responsive to a voltage on the first single-wire link being above a predetermined threshold voltage, enabling charging activity using the voltage on the first single-wire link;

A second circuit including a second input/output interface for communicating via a second single-wire link;

A dual port circuit coupled between the first circuit and the second circuit, the dual port circuit comprising: a first interface for communicating with a first circuit via the first single wire link; a second interface for communicating with the second circuit via the second single-wire link, one of the first single-wire link and the second single-wire link being enabled for single-wire data communication at a given time, the first interface and the second interface establishing a bi-directional level transition between the first circuit and the second circuit in a pass-through mode upon activation; and

A buffer in communication with the first single-wire link and the second single-wire link and configured to transmit data during single-wire communication.

9. The system of claim 8, wherein the buffer and the dual port circuit are integrated within a single chip.

10. The system of claim 9, wherein the single chip and the second circuit are combined together into a single device.