MXPA00003423A - Digital convergence correcting device and display device - Google Patents

Abstract

The deterioration of the correction accuracy of a digital convergence correcting device which occurs when the relation between a screen raster and an effective area of picture changes is prevented. The vertical displaying range detecting signal corresponding to the vertical position of a video displaying range on the screen is generated based on a vertical deflecting current and an address counter which generates the reading-out address of correcting data is controlled based on the detecting signal.

Description

DIGITAL CONVERGENCE CORRECTION DEVICE AND VISUALIZATION DEVICE Technical Field The present invention relates to a digital convergence correction device and to a display device comprising the digital convergence correction device. Prior Art Generally, in the digital convergence correction device, a plurality of points are established on a cathode ray tube screen to be the convergence correction points, and a convergence correction amount is preliminarily obtained in each point of convergence correction and stored in a memory as correction data. Then, the correction data is read from the memory synchronously with the screen scan, and the read correction data is converted into an analog signal. Then, a convergence correction signal is generated by interpolating (smoothing) the analog signal with a low pass filter, and a convergence yoke coil (CY coil) of the cathode ray tube is driven. The amount of convergence correction is a determined value depending on a position on the cathode ray tube screen. That is, the amount of convergence correction corresponds to (is associated with) a position on the cathode ray tube screen in a one-to-one ratio. Therefore, the plurality of convergence correction points are predetermined to correspond to the position on the cathode ray tube display in a one-to-one ratio, and with respect to each convergence correction point, the The amount of convergence correction obtained preliminarily is stored in the memory as correction data. In accordance with the above, if a ratio between an effective image area that is an effective display region on the cathode ray tube screen and a screen browser that is a region of scanning on the cathode ray tube screen varies , then the problem arises that the correction data read synchronously with the screen scan fails to correspond with the convergence correction points on the cathode ray tube screen. For example, this problem arises in the case where the screen browser is enlarged in the direction of otherwise reduced over-scan in the sub-scan direction, or in the case where the aspect ratio of the screen browser varies , or in the case where the screen browser is vertically offset or & ^^ l ^ horizontally within the effective area of the image. Particularly, in the display device capable of inputting an image signal of different scanning frequency, a relationship between the screen browser and the effective cathode ray tube image area may vary due to the variation in the offset frequency. In this case, it is impossible to perform the convergence correction in an appropriate manner. Japanese Open Patent Publication No. 33791/1985 discloses a digital convergence correction device capable of performing a convergence correction even if the relationship between the screen browser and the effective cathode ray tube image area varies . This convergence correction device comprises a memory for storing correction data for each scanning frequency and a low pass filter for each scanning frequency, and is used by detecting a frequency of the input image signal and selecting a memory and a filter low step corresponding to the scan frequency detected. However, to perform the convergence correction properly, it is necessary to provide a large number of convergence correction points on the cathode ray tube screen. To store the correction data for each convergence correction point, it is -. * __. it requires a large capacity memory. In accordance with the foregoing, there is a problem that the convergence correction device provided with this memory for each scanning frequency is expensive, and the display device is also expensive. There is another problem which is a result of providing a low pass filter corresponding to each scanning frequency, the circuits are complicated and, therefore, the convergence correction device is expensive and the display device is more expensive. Moreover, in a conventional convergence correction device, since the relationship between the screen browser and the effective area of the image is specified by a scan frequency, if the relationship between the screen browser and the effective area of the Cathode ray tube image is different when an identical scan frequency image signal is input, there is another problem that any convergence correction can not be performed properly. On the other hand, the Open Patent Publication Japanese (unexamined) number 20809/1995 discloses a relatively reasonable cost digital convergence correction device that performs a convergence correction for an image signal of different scanning frequency. In this correction device ^ '% convergence, without synchronization with the screen scan, the correction data is read from a memory with a certain period. In accordance with the above, even if any image signal of different scanning frequency is entered, the time interval for reading the correction data may be constant, and without changing any low pass filter, it is possible to correspond to the signal of image of different frequency. That is, since this convergence correction device comprises only a low pass filter, it is possible to provide a relatively reasonable cost convergence correction device capable of matching a different scanning frequency. However, the aforementioned problem that a large capacity memory is required still remains unresolved. Furthermore, in the case where the relationship between the screen browser and the effective image area is different, it is impossible to perform any convergence correction in an appropriate manner. DESCRIPTION OF THE INVENTION A digital convergence correction device according to the invention comprises: a memory for storing correction data for each convergence correction point corresponding to a position on the screen in a one-to-one relationship, and a address counter to generate a read address with respect to the memory synchronously with screen scan; and in which a convergence correction signal is generated according to the correction data read; the aforementioned digital convergence correction device comprising: a vertical display area detection circuit for generating and producing a vertical display area detection signal corresponding to a position in the vertical direction of an image display area on the screen according to a vertical deflection current; and an address control circuit for controlling an address counter according to the vertical display area detection signal. In the digital convergence correction device of the above configuration, controlling the address counter according to the detection signal of the vertical display area corresponding to a position in the vertical direction of an image display area on the screen, it is possible to read the correction data from the memory corresponding to the image display area on the screen. As a result, even if a relationship between a screen browser and an effective area of the image varies with respect to the vertical direction, a convergence correction can be made very precisely. That is, even in the case of over-scanning, it is possible to read the memory correction data synchronously with screen scanning so that it corresponds to each convergence correction point corresponding to a "position on the screen in the ratio In the digital convergence correction device according to the invention, the vertical display area detection circuit comprises a comparator for comparing a current value of the vertical deflection current with a predetermined comparison level, and in the case of under-scanning, a level corresponding to positions of two extremes in the vertical direction of a screen browser is used as a level of comparison, and in the case of over-scanning, a level corresponding to positions of two extremes in the vertical direction of an effective area of image is used as a level of comparison.As a result, even if a relationship between the former screen saver and the effective area of the image varies with respect to the vertical direction it is possible to generate a vertical display area detection signal corresponding to a position in vertical direction of the image display area, thus it can be carried out a desired convergence correction. In the digital convergence correction device according to the invention, the address circuit preliminarily stores the vertical display area detection signal in the case of over-scanning as a vertical effective image area signal, and in the case of of underexploration, a time delay is obtained between a timing of the variation in the vertical effective area image signal and a timing of variation in the vertical display area detection signal, and the time delay becomes an address of reading and is produced for the address counter. As a result, even if a relationship between the screen browser and the effective area of the image varies with respect to the vertical direction, a desired convergence correction can be carried out. That is, even in the case of sub-scanning, it is possible to read the correction data from the memory synchronously with screen scanning so that it corresponds to each convergence correction point corresponding to a position on the screen in the ratio of one to the other. one. The digital convergence correction circuit according to the invention comprises a signal generation signal circuit to produce a display area indication signal indicating an image display area in vertical direction on the screen according to the signal Detection of vertical display area. As a result, it is possible to display a display area indication signal with respect to the vertical direction, and easily obtain a vertical display area detection signal when a position in the vertical direction of the screen browser coincides with a position in the direction vertical of the effective area of the image. A display device according to the invention comprises the aforementioned digital convergence correction device having an indication signal generation circuit for producing a display area indication signal in accordance with the vertical display area detection signal , and an image display circuit for displaying an image according to the display area indication signal from the digital convergence correction circuit. As a result, it is possible to display on the screen a display area indication signal with respect to the vertical direction, and to easily obtain a vertical display area detection signal when a position in the vertical direction of the screen browser coincides with a position in the vertical direction of the effective area of the image. In the digital convergence correction device according to the invention, in the case of over-scanning, the steering control circuit produces a read direction during a first period of horizontal scanning to the address counter for each horizontal scanning period, from a time of variation in the vertical synchronization signal to a variation time in the detection signal of the vertical display area, according to the vertical synchronization signal and the vertical display area detection signal. As a result, in the case of over-scanning, the convergence correction signal varies suddenly in and around the upper end of the image display area on the screen, whereby the displayed image may be prevented from becoming disordered. In the digital convergence correction device according to the invention, in the case of over-scanning, the direction control circuit produces a read direction during a final horizontal scanning period to the address counter for each horizontal scanning period. , from a time of variation in the vertical synchronization signal to a time of variation in the display area detection signal, according to the vertical synchronization signal and the detection signal of the vertical display area. As a result, in the case of over-scanning, the convergence correction signal suddenly varies in and around the lower end of the image display area on the screen, whereby the display image may be prevented from becoming disordered. The display device according to the invention comprises the correction device of .faith. digital convergence mentioned. As a result, even if the relationship between the screen browser and the effective area of the image varies with respect to the vertical direction, there is no decrease in the accuracy of the convergence correction, and an image display can be carried out. high quality. A digital convergence correction device according to the invention comprises: a memory for storing correction data for each convergence correction point corresponding to a position on a screen in a one-to-one relationship, and an address counter for generate a read address with respect to the memory synchronously with screen scanning; and in which a convergence correction signal is generated according to the correction data read; said digital convergence correction device comprising: a horizontal display area detection circuit for generating and producing a horizontal display area detection signal corresponding to a position in the horizontal direction of an image display area on the screen according to a horizontal deflection current; and an address control circuit for controlling an address counter according to the horizontal display area detection signal. In the convergence correction device Z * haSí. digital of the above configuration, by controlling the address counter according to the detection signal of the horizontal display area corresponding to a position in the horizontal direction of an image display area on the screen, it is possible to read the correction data from the corresponding memory to the image display area on the screen. As a result, even if a relationship between the screen browser and the effective area of the image varies with respect to the horizontal direction, a convergence correction can be carried out very accurately. That is, even in the case of over-scanning, it is possible to read the correction data from the memory synchronously with the screen scan so that it corresponds to each convergence correction point corresponding to a position on the screen in the ratio from one to one. In the digital convergence correction device according to the invention, the horizontal display area detection circuit comprises a comparator for comparing a current value of the horizontal deflection current with a predetermined comparison level, and in the case of underexploration , a level that corresponds to positions of two extremes in the horizontal direction of the screen browser is used as a level of comparison; and in the case of over-exploration, a level corresponding to positions of two extremes in the horizontal direction of the effective area of Sv | / image as a level of comparison. As a result, even if a relation between the screen browser and the effective area of the image varies with respect to the horizontal direction, it is possible to generate a detection signal of the horizontal display area corresponding to a position in the horizontal direction of the display area. image display, in this way a desired convergence correction can be carried out. In the digital convergence correction device according to the invention, the address circuit preliminarily stores the horizontal display area detection signal in the case of over-scanning as a horizontal effective area signal of the image, and in the In the case of underexploration, a time delay is obtained between a timing of variation in the horizontal effective image area signal and a variation timing in the horizontal display area detection signal, and the time delay becomes an address read and produced to the address counter. As a result, even if a relationship between the screen browser and the effective area of the image varies with respect to the horizontal direction, a desired convergence correction can be carried out. That is, even in the case of sub-scanning, it is possible to read the correction data from the memory synchronously with screen scanning so that it corresponds to each convergence correction point corresponding to a position on the screen in the ratio of one to the other. one. The display device according to the invention comprises the mentioned digital convergence correction device. As a result, even if the relationship between the screen browser and the effective area of the image varies with respect to the horizontal direction, there is no decrease in precision of the convergence correction, and a high-resolution image display can be carried out. quality. The digital convergence correction circuit according to the invention comprises a signal generation signal circuit for producing a display area indication signal indicating an image display area in the horizontal direction on the screen according to the signal of detection of horizontal viewing area. As a result, it is possible to display a display area indication signal with respect to the horizontal direction, and easily obtain a horizontal display area detection signal when a position in the horizontal direction of the screen browser coincides with a position in the horizontal direction of the effective area of the image. A display device according to the invention comprises the aforementioned digital convergence correction device having a signal generation signal circuit for producing a display area indication signal in accordance with the horizontal display area detection signal , and an image display circuit for displaying an image according to the display area indication signal from the digital convergence correction circuit. As a result, it is possible to display on the screen a display area indication signal with respect to the horizontal direction, and to easily obtain a horizontal display area detection signal when a position in the horizontal direction of the screen browser matches a horizontal direction. position in the horizontal direction of the effective area of the image. A digital convergence correction device according to the invention comprises: a memory for storing correction data for each convergence correction point corresponding to a position on a screen in a one-to-one relationship, and an address counter for generate a read address with respect to memory synchronously with screen scan; and in which a convergence correction signal is generated according to the correction data read; The aforementioned digital convergence correction device is characterized in that it comprises: a circuit of ..- á-¿-t vertical display area detection to generate and produce a vertical display area detection signal corresponding to a position in the vertical direction of the image display area on the screen according to a current of vertical deviation; a horizontal display area detection circuit for generating and producing a horizontal display area detection signal corresponding to a position in horizontal direction of the image display area on the screen according to a horizontal deflection current; and an address control circuit for controlling an address counter according to the vertical display area detection signal. In the digital convergence correction device of the above configuration, generating the detection signal of the vertical display area and the horizontal display area detection signal and controlling the address counter according to these signals, it is possible to read the data of correction from the memory corresponding to the image display area on the screen. As a result, even if a relationship between the screen browser and the effective area of the image varies with respect to any of the vertical and horizontal directions, a convergence correction can be carried out very accurately. This is, even in the case of In the case of over scanning, it is possible to read the memory correction data synchronously with screen scanning so that they correspond to each convergence correction point corresponding to a position on the screen in the one-to-one ratio. In the digital convergence correction device according to the invention, the vertical display area detection circuit comprises a comparator for comparing a current value of the vertical deflection current with a predetermined comparison level, and in the case of underexploration , a level corresponding to positions of two extremes in the vertical direction of the screen browser is used as a comparison level, and in the case of over-scanning, a level corresponding to positions of two ends in the vertical direction of the effective area of the image is used as a comparison level, - and the horizontal display area detection circuit comprises a comparator for comparing a current value of the horizontal deviation current with a predetermined comparison level, and in the case of sub-scanning, a level that corresponds to positions of two ends in the horizontal direction of the screen browser is use as a level of comparison, and in the case of over-exploration, a level that corresponds to positions of two ends in the horizontal direction of the effective area of the image is used as a level of comparison. As a result, even if a relationship between the screen browser and the effective area of the image varies, it is possible to generate a vertical display area detection signal corresponding to a position in the vertical direction of the image display area and generate a horizontal display area detection signal corresponding to a position in the horizontal direction of the image display area, thus a desired convergence correction can be made. In the digital convergence correction device according to the invention, the address circuit preferably stores the vertical display area detection signal in the case of over-scanning as a vertical effective area signal of the image and the circuit of address preliminary stores the horizontal display area detection signal in the case of over-scanning as a horizontal effective image area signal, and - in the case of under-scanning, a time delay between a timing of variation in the signal of vertical effective area of the image and a timing of variation in the detection signal of vertical display area is obtained and a time delay between a timing of variation in the horizontal effective image area signal and a variation timing in the display area detection signal horizontal is obtained; and the delays become a read address and are produced for the address counter. As a result, even if a relationship between the screen browser and the effective area of the image varies with respect to any of the vertical or horizontal directions, a desired convergence correction can be made. That is, even in the case of underexploration, it is possible to read the correction data from the memory synchronously with the screen scan so that it corresponds to each convergence correction point corresponding to a position on the screen in the ratio of one to one. The display device according to the invention comprises the mentioned digital convergence correction device. As a result, even if the relationship between the screen browser and the effective area of the image varies with respect to some of the horizontal direction or the vertical direction there is no decrease in the accuracy of the convergence correction and the high quality image display. The digital convergence correction circuit according to the invention comprises a siggeneration sigcircuit for producing a display area indication sigindicating a display area of ^^^ ~ J? image in the vertical direction of the screen according to the detection sigof the vertical display area and the detection sigof the horizontal display area. As a result, it is possible to display a display area indication sigwith respect to both a vertical and horizontal direction, and easily obtain a vertical display area detection sigand a horizontal display area detection sigcoincident with the area effective of the image. A display device according to the invention comprises the aforementioned digital convergence correction device having an indication siggeneration circuit for producing a display area indication sigin accordance with the vertical display area detection sigand the horizontal display area detection sig and an image display circuit for displaying an image according to the display area indication sigfrom the digital convergence correction circuit. As a result, it is possible to display on the screen a display area indication sigwith respect to both the vertical and horizontal directions, and to easily obtain a vertical display area detection sigand a matching horizontal display area detection sig with the effective area of the image.

F1 J £ X. ÉLS Brief description of the drawings Figure 1 is a block diagram schematically showing a display device arrangement according to example 1. Figure 2 is a block diagram showing an example configuration of a convergence correction circuit Bl shown in Figure 1. Figures 3 (a), (b) and (c) are explanatory diagrams explaining the operation of a memory 6 and a latch (latching circuit) of a bit 7 Figure 3 (a) is a diagram showing a specific configuration of a one bit 7 latch. Figure 3 (b) is a diagram showing that data is read from memory 6 in order and converted into data serially. Figure 3 (c) is a view showing that each of the series data corresponds to a position of the cathode ray tube screen in a one-to-one ratio. Figure 4 is a block diagram showing an example of an array of digital-to-ag converter (DAC) of one bit (8) shown in Figure 2. Figure 5 is a time diagram showing the variation in the Main sig in the one bit digital / ag converter (8) shown in Figure 4 when the gate impulse is at a high level all the time. Figure 6 (A) and (B) are time diagrams showing each variation in the main signals of the one-bit analog / digital converter (8) shown in Figure 2 in the case of two different horizontal deviation frequencies. Figure 6 (B) shows that a whitening pulse H_BLK is introduced, of which the frequency is half that of Figure 6 (A). Figure 7 is a diagram showing an example of an essential part of the digital convergence correction device according to example 2 and is a circuit diagram showing an arrangement of a gate impulse generation circuit 13 shown in FIG. Figure 1. Figure 8 is a timing diagram showing the variation in the main signals in a gate pulse generation circuit shown in Figure 7. Figure 9 is a block diagram showing an example of an essential part of the display device according to example 3, and is a block diagram showing another arrangement of the digital convergence correction device shown in Figure 1. Figure 10 is a block diagram showing an example of an array of a digital / analog bit converter (FIG. 8A) shown in Figure 9. Figure 11 is a timing diagram showing the variation of the main signals in the one-bit digital / analog converter shown in Figure 10 in the case of variation in the frequency of exploration. Figures 12 (a) and (b) are each seen showing an example of a display area. Figure 12 (a) shows an overexplorer in which a screen browser is larger than the effective image area of a cathode ray tube, and Figure 12 (b) shows a subexplorer in which the screen browser is less than the effective area of the image of a cathode ray tube. Figure 13 is a block diagram schematically showing a configuration of a display device according to example 4. Figure 14 is a diagram showing an example of a diversion current detection circuit configuration El and E2 shown in Figure 13. Figure 15 is a diagram showing another example of an array of the deflection current detection circuits El and E2 shown in Figure 13. Figure 16 is a block diagram showing an example of a configuration of a convergence correction circuit B2 shown in Figure 13. Figure 17 is a diagram showing an example of a configuration of a vertical display area detection circuit 17 shown in Figure 16. Figure 18 is a diagram showing an example of a variation in each signal of the area detection circuit vertical display 17 shown in Figure 17. Figure 19 is a diagram showing an example of a configuration of a horizontal display area detection circuit 18 shown in Figure 16. Figure 20 is a diagram showing an example of a variation in each signal of the detection circuit of the horizontal display area 18 shown in Figure 19. Figure 21 (a) to (c) are explanatory views of a detection signal of the vertical display area V_DIS and a signal of horizontal display area detection H_DIS. Figure 21 (a) shows an over-scan, Figure 21 (b) shows a sub-scan, and Figure 21 (c) shows that the screen browser matches the effective area of the image. Figures 22 (a) and (b) are explanatory views for explaining an operation of the address control circuit 19 in the underexploration state. Figure 22 (a) shows a time delay in timing in the vertical direction, and Figure 22 (b) shows a time delay in timing in the horizontal direction. Figures 23 (a) and (b) are diagrams each showing an example of a relationship between the display area and correction data in memory 6 (memory address mapping). Figure 23 (a) shows a memory address mapping in the over-scan state, and the j ^ jj ^ É Figure 23 (b) shows a memory address mapping in the underexploration state. Fig. 24 is a block diagram showing an example of a one bit digital / analog converter (8B) configuration shown in Fig. 16. Fig. 25 is a block diagram schematically showing a configuration of a digital device. display according to example 5. Figure 26 is a block diagram showing an example of a configuration of a digital convergence correction circuit B3 shown in Figure 25. Figure 27 is a block diagram showing an example of a configuration of an indication signal generating circuit 20 shown in Figure 26. Figure 28 shows that an image display circuit A2 shown in Figure 25 exhibits a display area indication signal HV_CSL on a display screen of cathode ray tube, along with the main signals. Figure 29 is a diagram showing an example of an essential part of a display device according to example 6, and is a block diagram showing another example of a configuration of the digital convergence correction device B3 shown in FIG. Figure 25. Figure 30 is a block diagram showing an example of an array of a digital / analog converter of a bit (8C) shown in Figure 29. Figure 31 is a diagram showing an example of an essential part of a display device according to example 7, and is a block diagram that shows another example of a configuration of the digital convergence correction device B3 shown in Figure 25. Figure 32 is a timing diagram for explaining an example of an operation of an address control circuit 19A shown in Figure 31, and shows a variation in the main signals from a first transition (leading edge) of a vertical bleaching pulse V_BLK to a last transition (trailing edge) of a vertical display area detection signal V_DIS. Figure 33 is a timing diagram for explaining an example of an operation of the address control circuit 19A shown in Figure 31, and shows a variation in the main signals from a last transition of the vertical bleed pulse V_DIS to a first Transition of vertical area detection signal 20 V_BLK. Fig. 34 is an explanatory view showing schematically on a screen a result of the operation of the address control circuit 19A shown in Figs. 32 and 33. Fig. 35 is a diagram showing an example of a configuration of a display device according to example 8. Figure 36 is a block diagram showing an example of a configuration of a convergence correction device B4 shown in Figure 35. Figure 37 is a diagram that shows an example of a correction point indication pattern L_CSL displayed on a screen by an image display circuit A3 together with the vertical display area detection signal V_DIS and the horizontal display area detection signal H_DIS. Figure 38 is a diagram showing an example of an adjustment order with respect to each 25-point convergence correction point shown in Figure 37. Figure 39 is a block diagram showing schematically an example of a configuration of a display device according to example 9. Figure 40 is a block diagram showing an example of a configuration of a convergence correction device B5 shown in Figure 39. Best way to carry out the invention Example 1 Figure 1 is a block diagram schematically showing a configuration of a display device according to example 1. In the drawing, the . tS it. reference numeral Al indicates an image display circuit, numeral Bl indicates a convergence correction circuit, numeral C indicates a cathode ray tube, numeral Cl indicates a deviation yoke, and numeral C2 indicates a yoke of convergence. The image display circuit Al is a circuit for displaying an image on the cathode ray tube screen according to an input picture signal. The image display circuit Al supplies a vertical deflection current iDYV and a horizontal deflection current iDYH to the deflection yoke Cl, and it supplies a color signal to a cathode cathode tube cathode. The convergence correction circuit Bl supplies a convergence correction current iCY to the convergence yoke C2 in accordance with a horizontal bleaching pulse H_BLK and a vertical bleaching pulse V_BLK from the image display circuit Al, and corrects an angle of deviation of an electron beam. Figure 2 is a block diagram showing an example of the convergence correction circuit circuit Bl shown in Figure 1. In the drawing, the reference numeral 1 indicates an input terminal of the horizontal bleaching pulse H_BLK, the numeral 2 indicates an input terminal of the vertical bleed pulse V_BLK, and the numeral 3 indicates a phase locked phase circuit (PLL). Numeral 4 indicates a division counter, numeral 5 indicates > ** - U «ÉÉÍÉUÍ -ÉÉÉ¡i ^ É¿É = a = 1 ^ é_ an address counter, and the numeral 6 indicates a memory. The numeral 7 indicates a single-bit lock, the numeral 8 indicates a digital / analog one-bit converter, and the numeral 9 indicates a low-pass filter. The numeral 10 indicates an amplifier, the numeral 11 indicates an output terminal of a convergence correction current iCY, and the numeral 13 indicates a gate pulse generation circuit. [1] First, the elements shown in Figure 2 will be described later in the present. The horizontal bleaching pulse H_BLK of a frequency fH that is synchronized with the scanner on the cathode ray tube is input to the input terminal 1 H_BLK, and the secured phase cycle circuit 3 generates a reference clock by multiplying the pulse of horizontal bleaching H_BLK. In addition, the division counter 4 divides the reference clock and generates a system clock. As a result, the system clock controls division in the horizontal direction so that it is constant all the time. The address counter 5 is synchronized with the system clock, and generates the read addresses of the memory 6 in order. These addresses correspond to time phases in the horizontal direction and in the vertical direction of the browser, that is, for relative positions in the screen browser, respectively. The vertical whitening pulse V_BLK of a frequency fy that is synchronized dllÍMÜ-li ^ jjj with the scanner in the cathode ray tube is inserted into the terminal input 2 of V_BLK, and the horizontal bleed pulse V_BLK establishes the address counter 5. The memory 6 preliminarily stores a correction amount in each convergence correction point corresponding to a position on the cathode ray tube screen in a one-to-one ratio as correction data. These correction data are up / down information (variation information) at the time when the amount of correction at the corresponding convergence correction point is compared to a correction amount of an adjacent convergence correction point in the horizontal direction. Each of the correction data comprises one bit, and "1" indicates "increase" in the correction amount and "0" indicates "reduction" in the correction amount. In this way, the capacity of the memory to store the correction data is greatly reduced compared to the conventional convergence correction device in which the correction amount is stored and saved for each convergence correction point. The one bit correction data can be used together with an adjacent correction data as a two bit link pattern. More specifically, an information up / down to a convergence correction point can represent three states of "increase", "decrease", "constant" .... ^ ^ ¿z. , mt ^^ '^, i,. ^ ...,,. .,, .. ^ ^. in the form of two-bit up / down information, combining one-bit correction data corresponding to the convergence correction point and one-bit correction data corresponding to the adjacent convergence correction point. As the two bit link pattern, there are four types of combinations of "00", "01", "10", and "11". Among them, "01" or "10" represents that the "constant" correction amount, "00" represents "reduction" in the correction amount, and "11" represents "increases" in the correction amount. Generally there is no sudden variation in the amount of convergence correction such as variation from "increase" to "decrease" or from "decrease" to "increase". In accordance with the foregoing, by preliminarily fixing a sufficient number of convergence correction points on the cathode ray tube screen, any desired convergence correction can be made using the correction data as the aforementioned link pattern. The correction data are read from the memory 6 according to the address from the address counter 5. This is, since the reading of the memory 6 is performed synchronously with the cathode ray tube scanner, the correction data read they correspond to the convergence correction point, insofar as the relationship between the effective area of the image and the screen browser remains unchanged.

Since each of the correction data is one bit, when the bit width of the memory 6 is 8 bits, the correction data for eight convergence correction points can be stored in one direction, and the 8 data of the correction data can be stored in one direction. Correction can be read simultaneously. The one-bit latch 7 is a circuit for converting the data read from the memory 6 into serial data and comprises a phase shift transistor. For example, when the 8-bit data is read from memory 6, the data is divided into one bit correction data for each convergence correction point, and is output from the most significant bit side (MSB) in order as serial data synchronously with those of the system. Figures 3 (a), (b) and (c) are explanatory diagrams explaining the operation of a memory 6 and a one-bit latch 7. Figure 3 (a) is a diagram showing a specific configuration of a latch of a bit 7. Figure 3 (b) is a diagram showing that data is read from memory 6 in order and converted into serial data. Figure 3 (c) is a view showing that each of the series data corresponds to a position of the cathode ray tube screen in a one-to-one ratio. As shown in Figures 3 (b) and (c), the correction data is read in order for the convergence correction points in the first horizontal scan line on the screen and converted into serial data. j ^^^^ & g ^^ Figure 4 is a block diagram showing an example configuration of a digital / analog bit converter (8) shown in Figure 2. In the drawing, the reference numeral 80 indicates a decoding circuit for converting serial data into a signal above and a signal below. The numeral 81 indicates a gate circuit for controlling the output time of the signal above and the signal below that is constant regardless of the scan frequency. The numeral 82 indicates a subtraction circuit for converting the signal above and the signal below in an up-down signal. Numeral 83 indicates an integration circuit to integrate the up-down signal. The decoding circuit 80 comprises D tilters 801 to 803 and NOR operation circuits 804 and 805. The tilter 801 generates the phase gate signals gl and g2 by inverting synchronously with the first transition of the system clock. These phase gate signals gl and g2 are inversion signals with respect to each other. The phase gate signals gl and g2 become timing signals CLK1 and CLK2 respectively through a ÑOR operation with a system clock in the operation circuits ÑOR 804 and 805. The jogger 802 synchronizes with the timing signal CLK1 and the toggle 803 that synchronizes with the timing signal CLK2 respectively stores one bit serial data. Then, the jogger ^^ 802 takes out the stored data as a signal above, while the 803 jogger inverts the stored data and outputs them as a signal below. The gate circuit 81 comprises "AND" operation circuits (AND) 810 and 811. The signal above and the signal below are subjected to an AND operation with a last gate pulse described respectively and the operation circuits AND 810 and 811, and they are introduced to the subtraction circuit 82. That is, only when the gate pulse is at a high level, the signal above and the signal below can pass through the gate circuit 81. The subtraction circuit 82 comprises an operational amplifier and resistors, and generates a signal up-down subtracting the signal above passed through the gate circuit from the signal down past through the gate circuit 81. In accordance with the above, this signal up-down is a signal comprising three voltage levels; of level -1 representing the "increase", level +1 representing the "reduction", and level ± 0 representing the "constant". The integration circuit 83 is a mirror integration circuit that uses an operational amplifier, and produces an analog signal obtained by integrating the up-down signal. This analog signal becomes a continuous convergence correction signal in the low pass filter *_BI-. ^ * e * ¿. . ,, ^ .. ^ 9, and after being amplified in the amplifier 10, it is supplied to the convergence yoke coil C2. Using this one bit (8) digital / analog converter, it is possible to convert a 2-bit link pattern into top-down information, and obtain the desired amount of correction at each convergence correction point. [2] Now, the operation of the convergence correction circuit Bl when the gate pulse is at a high level all the time will be described hereinafter. Figure 5 is a timing diagram showing the variation in the main signals in the one-bit digital / analog converter (8) shown in Figure 4 when the gate pulse is at a high level all the time. In the drawing, the reference symbol (a) indicates the serial data, (b) indicates a system clock, (c) indicates a phase gate signal gl, and (d) indicates a phase gate signal g2 . The symbol (e) indicates a clocking signal CLK1, (f) indicates a timing signal CLK2, (g) indicates a signal above, and (h) indicates a signal below. The symbol (i) indicates a gate impulse, (j) indicates an up-down signal, and (k) indicates an analog output signal. The timing signals CLK1 and CLK2 produce pulses alternately and synchronously with the system clock. The signal above is renewed synchronously with the timing signal CLK1, and the signal below is renewed _ ^ tfÍÉmÉte. synchronously with the timing signal CLK2. In this case, since the gate pulse is at a high level all the time, both the signal above and the signal below pass through the gate circuit 81 all the time, and a result of the subtraction of these signals becomes an up-down signal. Therefore, during the period when the link pattern of the serial data is "01" or "10", the output level of the analog output signal is constant without variation. During the period of "00", the output level continuously decreases, and during the period of "11", the output level increases continuously. [3] Now, the operation of display device when the frequency of deviation varies will be described hereinafter. Figures 6 (A) and (B) are time diagrams each showing variation in the main signals of the one-bit digital / analog converter (8) shown in Figure 2 in the case of two different horizontal deviation frequencies. Figure 6 (B) shows that a whitening pulse H_BLK whose frequency is half that of Figure 6 (A) is introduced. Note that in Figures 6 (A) and (B), the abscissa axis is common, that is, it is shown on the same time scale. The system clock is a signal obtained by multiplying the horizontal bleaching pulse entered and dividing it, and the frequency of the same varies in proportion to , _ »-. ", ^ -,.« _ ^? . JHBffpg ii < - * - ~? , _-...... a horizontal deviation frequency fH. In accordance with the foregoing, when the horizontal deviation frequency fjj becomes 1/2 (half), the horizontal address counter 6 generates an address with the frequency of 1/2, and the reading of the correction data of the memory 12 is also performed with the frequency of 1/2. As a result, in the case of Figure 6 (B), both the system clock and the serial data vary with a period twice that of Figure 6 (A). On the other hand, the gate pulse generation circuit 13 is a monostable multivibrator that generates a gate pulse synchronously with the system clock, and the pulse duration of the gate pulse is constant all the time regardless of the system clock. In accordance with the above, while the gate impulse in Figure 6 (A) is at a high level all the time, the working rate of the gate impulse in Figure 6 (B) is 50 percent. Therefore, the period when the up-down signal is at the "reduction" level and the period when it is at the "increase" level are equal in both Figures 6 (A) and (B), and the integration periods in the integration circuit 83 they are also the same. As a result, even if the analog output signal extends in the direction of the time base, a W-type value can be kept constant all the time. 3d- That is, in this convergence correction device, the clock frequency of the system varies by the secured phase cycle circuit 3 in proportion to the variation in the horizontal deviation frequency, and the system clock maintains the division in a constant horizontal direction all the time. In accordance with the above, this does not cause time delay in the correspondence relationship between the reading timing of the correction data and the convergence correction point at which the data of correction should correspond. Even in the case of variation in the horizontal deviation frequency, the impulse duration of the gate pulse can be kept constant, and independently of the horizontal deviation frequency, the output time in the system clock period of the The output signal of the gate circuit 81 is kept constant. In this way, the level (ie the peak level) of the analog output signal corresponding to the convergence correction point is prevented from varying. As a result, even if the frequency of horizontal deviation varies, it is possible to perform a desired convergence correction with respect to each convergence correction point corresponding to a position on the cathode ray tube screen in a one-to-one ratio. Using the convergence correction device as described above, it is possible to greatly reduce the ádíUi - i_lHá-_ memory capacity to store and save the correction data. Furthermore, by determining a correction amount at each convergence correction point with respect to a horizontal deviation frequency, it is possible to perform a desired convergence correction without determining another correction amount with respect to another different horizontal deviation frequency. Although in this example 1 an example is described in which a horizontal deviation frequency is twice that of another horizontal deviation frequency, the convergence correction device according to the invention is not limited to this example. That is, in the convergence correction device according to the invention, a maximum applicable frequency is achieved when the duty ratio of the gate pulse is 100 percent. Therefore, the convergence correction device can be applied to any frequency of horizontal deviation within the area that does not part from the 100 percent work rate. Although the one-bit correction data is used in this example, it is possible to use 2-bit correction data. For example, using 2-bit data, each state of "increase", "reduction", or "constant" can be stored and maintained for each convergence correction point without using the data as the link pattern. It is also possible to store and maintain * ^^ £ ^ ag i¡j ^ .... > . ^ -, 1 tl |. [| F .. ^. 1 | Tl ^ ¡^ ^^ an "increase" of which the variation is of two graduations and a "reduction" of which the variation is of two graduations using 2-bit data. Example 2 Figure 7 is a diagram showing an example of an essential part of the digital convergence correction device according to example 2, and is a circuit diagram showing a configuration of the gate pulse generation circuit 13 shown in Figure 1. The gate pulse generation circuit 13 is a combinatorial tilt circuit. In the drawing, the reference numeral 130 indicates a tilter D with a reset terminal, the numeral 131 indicates a tristate damper capable of producing a high impedance, and the numeral 132 indicates an inverting Schmitt damper. R indicates a resistor, and C indicates a capacitor. Figure 8 is a timing diagram showing the variation in the main signals in the gate pulse generation circuit. In the drawings, (a) indicates a system clock, (b) indicates a gate pulse, (c) indicates a terminal voltage Vc of the capacitor, and (d) indicates a reset signal of the jogger. In the flip-flop 130, a high level is input from the source voltage Vccl to an input terminal D, and a trigger input terminal is input to a system clock. In accordance with the above, a terminal of ^ gg ^. + ..? * ^, > Q output comes at a high level synchronously with the first transition of the system clock, the high level is produced as a gate pulse, and an output terminal of the tri-state buffer 131 varies from a low level to a high impedance state. When the output terminal of the tristate buffer 131 reaches the high impedance state, a current i flows from the power source Vcc2 to the capacitor C through the resistor R, and the capacitor C is charged. Then, when the terminal voltage V ^ of the capacitor C reaches a threshold level Vm of the Schmitt damper inverter 132, the output terminal of the inverter damper Schmitt 132 varies at a low level, and the tumbler 130 is reset. When the jogger 130 is reset, the output terminal Q thereof varies at a low level, and the low level is produced as a gate pulse, and the output terminal of the tri-state buffer 131 reaches a low level. As a result, a current i 'flows from the capacitor C to the tristate damper 131, and the capacitor C is discharged, by which the output of the Schmitt damper inverter 132 varies at a high level. By repeating the aforesaid operation, it is possible to generate the gate pulse comprising constant pulse duration pulses synchronizing with the system clock. That is, it is possible to produce, synchronously with the scanning frequency, impulses of which the ^ * - «* - - = • - MJfefiJK > **** • - pulse duration is constant regardless of the scan frequency. The duration of each pulse forming the gate pulse corresponds to the charging time of the capacitor C and, therefore, the gate pulse can be set to have any desired pulse duration by selecting the voltage value of the power source Vcc2 , resistance value of resistor R and capacity. In addition, the pulse duration is easily adjusted using a variable power source such as the power source Vcc2 and controlling the output voltage thereof by means of a microcomputer (not shown). Example 3 When the scanning frequency is constant, the division counter 4 can supply a stable system clock. On the contrary, when the scanning frequency varies, the system clock becomes unstable due to the resetting of the secured phase cycle circuit 3, and the address supplied from the address counter 5 to the memory 6 is decomposed. As a result, each convergence correction point corresponding to a position on the screen in one-to-one relation does not correspond to the reading of correction data. In this way, the convergence correction signal iCY supplied to the convergence yoke coil C2 is decomposed, and the image display is decomposed. In this example, a display device is described to avoid any clutter in the image display due to the convergence correction signal, in the case of variation in the scanning frequency of the input image signal. Figure 9 is a block diagram showing an example of an essential part of the display device according to example 3, and is a block diagram showing an arrangement of the digital convergence correction device shown in Figure 1. This convergence correction device comprises the convergence correction device shown in Figure 2 to which the frequency detection circuit 12 is added, and a one bit digital / analog converter (8A) different from that of Figure 2. Figure 10 is a block diagram showing an example of a configuration of the one-bit digital / analog converter (8A) shown in Figure 9. This one-bit digital / analog converter (A) comprises the digital / analog converter of a bit shown in Figure 4 to which an inhibition circuit 84 is added, and in the drawing, the reference numeral 840 indicates an inverter (inversion operation circuit), the numeral 841 indicates an operation circuit AND, and the numeral 842 indicates an operation circuit "O" (OR). The circuit detection circuit 12 is a ^^ -. _ ^ -. ^^^^. ^ P ---------_ > , k ... f ... .___-_! _ - _-_ ,. .- and the circuit to monitor the variation in the scanning frequency, reset the phase locked cycle circuit 3 in the case of variation in frequency, and produce an inhibition signal to the digital / analog bit converter. (8A). This circuit can be formed on a microcomputer, for example. In this circuit, a horizontal bleaching pulse H_BLK and a vertical bleaching pulse V_BLK are introduced, and in the case of variation in the horizontal frequency and vertical frequency, the secured phase cycle circuit 3 is reset. In addition, a low level inhibition signal occurs only for a certain period after the variation in the horizontal frequency and the vertical frequency. When the inhibition signal is at a high level, the serial data passes through the AND 841 operation circuit and the OR 842 operation circuit and is, and operates in the same way as the one bit digital / analog converter in the Figure 4. When the inhibition signal reaches a low level, it produces an operation circuit AND 841 and the operation circuit OR 842 are set respectively to a low level and a high level, and both signals above and signal below are set at a low level The level of the analog output signal becomes constant. In the case where the scan frequency varies, the frequency detection circuit 12 produces a signal of «Á ^ dwfa" * ß * ¿-A * ¡U.? ». * Inhibition of a low level until the phase locked phase circuit 3 is restored and the system clock stabilizes. the convergence correction signal can be kept constant, and it becomes possible to avoid clutter in the image display Figure 11 is a timing diagram showing the variation in the main signals in the digital / analog bit converter shown in Figure 10 in the case of variation in scanning frequency When the inhibition signal varies from the high level to the low level due to the variation in the scanning frequency, both the signal above and the signal below are set to a low level, and the analog output signal is controlled to be constant.Then, after stabilizing the system clock, the frequency detection circuit 12 is controlled to again produce a one-level inhibit signal to, and to produce a desired analog signal. Although an example is described in Example 3 in which the convergence correction signal is controlled according to the variation in the horizontal frequency and the vertical frequency, it is also possible to make a control only according to the variation in the frequency horizontal or vertical. Example 4 In this example a device is described display capable of causing each convergence correction point to correspond to correction data read from memory 6, even in the case of variation in the ratio between the effective image area which is an effective display area on the display tube cathode rays and the screen explorer which is the area of exploration on the cathode ray tube screen. First, the image display area which is an area on the screen to view an image is described below, case by case depending on the relationship between the screen browser and the effective image area. With respect to this, it will be noted that in this example, the correction area, which is an area on the screen to perform the convergence correction, coincides with the image display area. Figures 12 (a) and (b) are each seen showing an example of display area. Figure 12 (a) shows an over-scan in which a screen browser is larger than an effective area of the image of a cathode ray tube, and Figure 12 (b) shows a subexploration in which the screen browser is smaller than the effective area of the image of a cathode ray tube. In the drawings, the solid line indicates an effective area of image, the broken line indicates a screen browser, and the shaded portion indicates a viewing area. As shown in the drawings, in the case of When the scan area is displayed, the display area is matched to the screen browser, and in the case of over-scanning, the display area is matched to the effective area of the screen. image. To perform a convergence correction with respect to this display area, in the case of sub-scanning, it is necessary to perform the convergence correction with respect to a part of the effective area of the image. Fig. 13 is a block diagram schematically showing a configuration of a display device according to this example 4. This display device comprises the display device shown in Fig. 1 to which current detection circuits are added. Deviation El and E2 to detect a current value of a deviation current, and a digital convergence correction circuit B2 different from that of Figure 1. The deviation current detection circuit El produces a detection signal DYV by detecting a current of vertical deflection iDYV, and the deflection current detection circuit E2 produces a detection signal DYH by detecting a horizontal deflection current iDYH. Then, the convergence correction circuit B2 produces a convergence correction signal iCY according to the detection signals DYV and DYH. Figure 14 is a diagram showing an example of "-" • - • '- l ^ MmrlT i- - ~ -a-ü - ... _ ^ ¿-tee-a- .. a configuration of deviation current detection circuits El and E2. In each of the deflection current detection circuits, a detection resistor RL is inserted in series with the deflection yoke Cl, and the voltage between the terminals of a detection resistor RL is made to be a detection voltage V0 . Using this circuit, the current flowing to the resistor RL, that is, the currents iDYV and iDYH flowing through the deflection yoke can be converted to the voltage values DYV and DYH. Figure 15 is a diagram showing another example of a configuration of the deflection current detection circuits El and E2. In this deflection current detection circuit, a coil on the primary side of a current transformer L for detection is connected in series with the deviation yoke Cl and the detection resistor RL is connected to the secondary side. The voltage between the terminals of the detection resistor RL is made to be a detection voltage V0. In this way, the deflection currents iDYV and iDYH can be converted into the voltage values DYV and DYH. Figure 16 is a block diagram showing an example of an array of a convergence correction circuit B2 shown in Figure 13. This convergence correction circuit comprises the convergence correction circuit shown in Figure 2 to which add a vertical display area detection circuit 17 for s- ^ »* Jl ** ÍAn. producing a vertical display area detection signal V_DIS, a display area detection circuit 18 for producing a horizontal display area detection signal H_DIS, and a 5-way control circuit 19 for controlling the address counter 5 , and a one bit digital / analog converter (8B) different from that of Figure 2. The vertical display area detection circuit 17 generates the detection area signal of vertical display V_DIS corresponding to the display area in the vertical direction according to the detection signal DYV of the vertical deflection current. The horizontal display area detection circuit 18 generates the display area detection signal Horizontal H_DIS corresponding to the display area in the horizontal direction according to the detection signal DYH of the horizontal deflection current. Figure 17 is a diagram showing an example of a configuration of a vertical display area detection circuit 17.

In this drawing, the reference numerals 170 and 171 indicate comparators, and the numeral 172 indicates a generation circuit V_DIS. Figure 18 is a diagram showing an example of a variation in each signal. In this drawing, (a) indicates the detection signal DYV, (b) indicates the output of the comparator 170, (c) indicates the output of comparator 171, and (d) indicates the detection signal of the display area V_DIS. The detection signal DYV of the vertical deflection current is compared to a level VT corresponding to the upper edge of the display area in the comparator 170, and compared to a level VB corresponding to the lower edge of the display area in the comparator 171 Then, according to the result of the comparison, the generation circuit V_DIS generates the detection signal of the vertical display area V_DIS corresponding to the display area in the vertical direction. Figure 19 is a diagram showing an example of a configuration of the horizontal display area detection circuit 18. In the drawing, the reference numerals 180 and 181 indicate comparators, and the numeral 182 indicates a generation circuit H_DIS. Figure 20 is a diagram showing an example of a variation in each signal. In the drawing, (a) indicates the detection signal DYH, (b) indicates the output of the comparator 180, (c) indicates the output of the comparator 181, and (d) indicates the detection signal of the horizontal display area H_DIS. The detection signal DYH of the horizontal deflection current is compared to a level VL corresponding to the left edge of the display area in the comparator 180, and compared to a level VR corresponding to the right edge of the display area in the comparator 181. Then , according to the result of the comparison, the generation circuit H_DIS generates the signal of gu jl * ^ ¡^. & & ^ - * J¿. ^: 7 ... «ri-i j-t,. ^". t_a «- ^ a-. detection of the horizontal display area H_DIS corresponding to the display area in the horizontal direction. Each of these comparative levels VT, VB, VR and VL is controlled and fixed by a microcomputer not shown. Figures 21 (a) through (c) are explanatory views of a vertical display area detection signal V_DIS and a horizontal display area detection signal H_DIS. Figure 21 (a) shows a new browser, Figure 21 (b) shows a sub-scan, and Figure 21 (c) shows that a screen browser matches the effective area of the image. In each drawing, with respect to the detection signal of the vertical display area V_DIS, the base time coinciding with the scale of the vertical scanner is indicated in the vertical direction. And with respect to the horizontal display area detection signal H_DIS, the base time coincident with the scale of the horizontal scanner is indicated in the horizontal direction. In the case of Figure 21 (b) and (c), it is sufficient for the microcomputer to control each level of comparison to establish the comparison levels VT and VB as a maximum value and a minimum value of the detection signal DYV respectively, and establishing the comparative levels VL and VR as a maximum value and a minimum value of the detection signal DYH respectively. On the other hand, in the case of Figure 21 (a), it is necessary to generate a vertical effective image area signal V_DISQ corresponding to the effective area of the image in vertical direction as the vertical display area detection signal V_DIS. It is also necessary to generate a horizontal effective image area signal H_DIS0 corresponding to the effective area of the image in the horizontal direction as the horizontal display area detection signal H_DIS. For that purpose, in the case of Figure 21 (c) in which the screen browser and the effective area of the image coincide, the microcomputer preliminarily stores the data of the vertical effective image area signal V_DIS0 and the data of the horizontal effective image area signal H_DISQ. Then, using this data, the microcomputer performs a control of each level of comparison in the state of over exploration. That is, in the case of over-scanning, the comparison levels VT and VB of the vertical display area detection circuit 17 are controlled so that the detection signal of the vertical display area V_DIS matches the signal data effective image area 0 vertical V_DISQ. And the comparison levels VL and VR of the horizontal display area detection circuit 18 are controlled so that the horizontal display area detection signal H_DIS coincides with the data of the horizontal effective image area signal H_DISQ. - ^ - ~ * *** * - • »» * "jgfe ^^ The address control circuit 19 controls the address counter 5 so that the correction data of a part of the memory 6 are read in the This sub-scan is performed in accordance with preliminarily examined data of the vertical effective image area signal V_DISQ, the previously stored data of the horizontal effective image area signal H_DIS0, the vertical display area detection signal V_DIS from the vertical display area detection circuit 17, and the detection signal of the horizontal display area H_DIS from the horizontal display area detection circuit 18. First, the address control circuit 19 obtains a time delay tV between the first transition in the vertical display area detection signal V_DIS and the first transition of the vertical effective image area signal V_DIS0, and conv the time delay obtained in an interval number nV of the convergence correction points in the vertical direction. The address control circuit 19 also obtains a time delay between the first transition of the horizontal display area detection signal H_DIS and the first transition of the horizontal effective image area signal H_DIS0, and converts the time delay obtained in an interval number nH (ie number of system clocks) of the convergence correction points in the horizontal direction. Figures 22 (a) and (b) are diagrams that each show a state. According to the result, the address control circuit 19 supplies a read address to the address counter 5. An address of the correction data corresponding to the convergence correction point which is (nV + 1) -th in the vertical direction and (nH + 1) -th in the horizontal direction is produced to the address counter 5. Also on the left edge of the screen browser, an address obtained by jumping nH convergence correction points in horizontal direction occurs for the address counter 5 The address counter 5 increments the addresses in synchronic order with the system clocks until the direction signal of the horizontal display area H_DIS varies at a low level after the address is set by the address control circuit 19. In the case of over-scanning, as all the correction data of the memory 6 were read, it is not necessary that the address control field 19 control the address counter 5. Figures 23 (a) and (b) are diagrams each showing an example of a relation of a display area and correction data in memory 6 (address mapping of memory) at the time of the aforementioned operation. Figure 23 (a) shows a memory address mapping in the ^^^^ ¡^^^ g ^ S ^ g ^ l ^^^ il ^ tj ^ ¿^^^^^ ^ ^ ^^^^? ^^^^^ state of over-exploration, and Figure 23 (b) shows a memory address mapping in the underexploration state. In the over-scan state, the convergence correction is made with respect to the entire effective area of the cathode ray tube image, and all the correction data stored in the memory 6 are used. On the other hand, in the of sub-scanning, the convergence correction is performed with respect to the entire screen browser, i.e. with respect to a part of the effective area of the image and only a part of the correction data stored in the memory 6 is used. In the drawings, it is shown that the memory 6 stores the correction data for all convergence correction points of the effective area of the image in the directions OOOOh to FFFFh, and in the state of its scanning, only the address data is used. 8888h to CCCCh. Figure 24 is a block diagram showing an example of a configuration of a digital / analog bit converter (8B). This one-bit digital / analog converter comprises the one-bit digital / analog converter (8) shown in FIG. 10 to which is added an initial value generating circuit 85, a digital / analog converter (86) and a circuit addition of current 87, and the address is supplied from the address counter 5. The initial value generating circuit 85 generates an amount convergence correction on the left edge of the screen browser in the underexploration state of a convergence correction amount on the left edge of the effective area of the image in the over scan state as an initial value data in accordance with the address from the address counter. This amount of convergence correction is a value obtained for each variation in the scanning frequency, and is an integration value of the correction data between the left edge of the effective area of the image and the left edge of the screen browser. The amount of convergence correction is stored in the memory of the voltage generation circuit. The initial value data from the initial value generating circuit 85 are converted to an analog signal and, added to the output of the integration circuit 83 in the addition circuit 87, becomes an analog output signal. Thus, in the case of over-scanning, the display device according to this example establishes the effective image area that is a viewing area and performs the convergence correction with respect to the effective area of the image. Therefore, each convergence correction point may correspond to the correction data read from the memory. 25 In the case of underexploration, the device ^^^ to ^ - - & i,. A ** ^ ^, .- tHMf rfjifilff '". -nMto.». ** * ^^ visualization of agreement as.}. This example performs convergence correction using a part of the correction data in memory, that is, using only the correction data z * corresponding to the convergence correction pui? ßfc) in the screen browser, therefore, each convergence correction point may correspond to the correction data read from the memory. Since the initial value of the correction amount is stored and maintained, also if the correction data is available data of the convergence correction amount, a correct analog output signal can be produced in the underexploration state. Convergence correction comprises the vertical display area detection circuit 17, the horizontal display area detection circuit 18, and the address control circuit 19. As a result In the same manner as in Example 4, the address counter 17 generates an address for the effective area of the image in the case of over-scanning, at the same time generating an address corresponding to each convergence correction point. in the screen browser in the case of underexploration. In accordance with the above, it is possible to perform a convergence correction at all times corresponding to the relationship between the screen browser and the effective area of the image. ^ ¡^^^ m ^ ^^.

As described in example 1, even in the case of variation in variation frequency, this convergence correction device can perform a desired convergence correction with respect to each convergence correction point corresponding to a position on the display of cathode ray tube in a one-to-one ratio. As a result, even if the relationship between the screen browser and the effective area of the image varies due to the variation in the scanning frequency, it is possible to perform a desired convergence correction. Also, not only in the case of the variation between the screen browser and the effective area of the image due to the variation in scanning frequency, but also in the case of the same scanning frequency, when the relationship between the scanner screen and the effective area of the image is different, a desired convergence correction can be made. Although the convergence correction in the case of typical over scan and underexploration can be described in this example 4, the convergence correction device is also applicable in the case where either the horizontal direction or the vertical direction is in the state of over-scan while the other is in the underexploration state. Example 5 In this example, a correction device of j * A * O? tet | g ^ convergence is able to easily obtain signal data from the vertical effective image area V_DISQ and data from the horizontal effective area signal H_DIS0. Figure 25 is a block diagram schematically showing an arrangement of a display device according to example 5. This display device comprises the display device shown in Figure 13 to which the image display circuit is added. A2 and a correction circuit digital convergence B3 different from those of Figure 13. The display area indication signal HV_CSL produced from the convergence correction circuit B3 is output to an image display circuit Al. And the image signal display circuit A2 performs a visualization image on the cathode ray tube (C) according to either an input image signal or a display area indication signal HV_CSL. Figure 26 is a block diagram showing an example of a configuration of a correction circuit of digital convergence B3 shown in Figure 25. This convergence correction circuit B3 comprises the convergence correction circuit shown in Figure 16 to which is added the indication signal generation circuit 20. The signal generation circuit of indication 20 generates the display area indication signal HV_CSL for - ^ ~ L. ** - * ¿~ - ± --- display a display area on the screen according to the display signal on the screen according to the detection signal of the vertical display area V_DIS and the detection signal of the area of horizontal display H_DIS. Figure 27 is a block diagram showing an example of a configuration of an indication signal generation circuit 20. In the drawing, the reference numeral 200 indicates a generation circuit V_CSL, the numeral 201 indicates a generation circuit H_CSL, and the numeral 202 indicates an OR operation circuit. The generation circuit V_CSL 200 produces the vertical display area indication signal V__CLS comprising pulses corresponding to two edges, that is, the upper edge and the lower edge of the display area in the vertical direction at the time of variation of the detection signal of the vertical display area V_DIS. Each pulse included in this vertical display area indication signal V__CLS has a sufficiently short pulse duration compared to the field period. In particular, it is preferable that each pulse has a pulse duration equivalent to a horizontal scanning period. The generation circuit H_CSL 201 produces the horizontal display area indication signal H_CSL which j ^ y ^ g comprises pulses corresponding to two edges, that is, the left edge and the right edge of the display area in the horizontal direction at a time of variation in the detection signal of the horizontal display area H_DIS. Each pulse included in this horizontal display area indication signal H_CSL has a sufficiently short pulse duration compared to the horizontal scan period. In particular, it is preferable that each pulse has a pulse duration equivalent to the system clock period. The OR operation circuit 202 mixes the vertical display area indication signal V_CSL and the horizontal display area indication signal H_CSL, and produces a display area indication signal HV_CSL corresponding to the peripheral edge of the display area. The image display circuit A2 displays this display area indication signal HV_CSL on the cathode ray tube screen as an image. That is, a rectangular frame-shaped image showing the peripheral edge of the display area is displayed. Figure 28 shows a relation between these signals, and shows a way in which the display circuit A2 exhibits the indication signal of the display area HV_CSL in the cathode ray tube display. A method is described later in this document - .__-_--. v £ * £ * & * .. * ^ * - ^ * ^^ MO ?? : M to obtain data of the vertical effective image area signal V_DIS0 and the data of the horizontal effective image area signal H_DISQ stored in the address control circuit 19. First, an input image signal is placed on the Over-scan status by changing the screen size of the display device or similar. At this time, each comparison level VT, VB, VL and VR that are to be controlled by the microcomputer are set to a value adapted to display all or part of the rectangular frame of the display area indication signal HV_CSL on the screen . As a result, the rectangular frame is displayed on the cathode ray tube screen by the image display circuit A2. In this way, an operator who sees the rectangular frame displayed on the screen controls the comparison levels VT and VB in the detection circuit of the vertical display area 17 and the comparison levels VL and VT in the detection circuit of the horizontal display area 18, so that the rectangular frame coincides with the peripheral edge of the effective area of the image. This control is done through a microcomputer not shown. By making the peripheral edge of the display area coincide with the peripheral edge of the effective area of the image, it is possible to produce the vertical effective image area signal V_DIS0 from the -é ^ ^ & í * &! »t ^ j-j-a-. _ .. _ ^ _ ^ -_ sz; | , tmmmMm \ -1i \ 7i HHiF ^ r T; r • »fteMMfc * htt * ~». € 3 detection of vertical display area 17 and produce the horizontal effective image area signal H_DISg from the detection circuit of the horizontal display area 18. In accordance with the above, the data can be obtained only by storing the output signal of the vertical display area detection circuit 17 obtained at this time as data of the vertical effective image area signal V_DISQ and storing the output signal of the detection circuit of the horizontal display area 18 as data of the area signal of effective horizontal image H_DIS0. Adopting the above configuration, the convergence correction device according to this example can easily obtain the data in the vertical effective image area signal V_DIS0 and the data of the horizontal effective image area signal H_DIS0. Although the indication signal generation circuit 20 produces the display area indication signal HV_CSL obtained by mixing the vertical display area indication signal V_CSL and the horizontal display area indication signal H_CSL in this example, it is also preferable that either the vertical display area indication signal V_CSL or the horizontal display area indication signal H_CSL is selectively produced to obtain the signal data of * i &i? i * iiai ______ i_ i. ^ _ ^ _ ^ ^ Z ^^ - »a6 vertical effective image area V_DIS0 and the horizontal effective image area signal data H_DIS0 in this order. EXAMPLE 6 In this example, a display device comprising the display device according to example 5 (FIG. 25) and able to avoid any disorder in the image display due to a disorder in the correction signal of the image is described. convergence even if the scan frequency of the input image signal varies. Figure 29 is a diagram showing an example of an essential part of the display device according to this example, and is a block diagram showing another example of a configuration of the correction device of The digital convergence shown in Figure 25. This convergence correction device comprises the convergence correction device shown in Figure 26 to which is added a frequency detection circuit 12, and a digital / analog bit converter. (8C) different from that of Figure 26. This frequency detection circuit 12 is a circuit equal to that shown in Figure 9. Figure 30 is a block diagram showing an example configuration of a digital / analog converter one bit (8C) shown in Figure 29. This converter digital / analog one bit (8C) comprises the converter one bit digital / analog (8B) shown in Figure 24 to which an inhibition circuit 84 is added. This inhibition circuit 84 is a circuit equal to that shown in Figure 10. In the case of variation in the scanning frequency , the frequency detection circuit 12 produces a low level inhibition signal until the secured phase cycle circuit 3 is restored and the system clock is stabilized. As a result, the inhibition circuit 84 sets the signal above and the signal down to a low level, and the analog signal of the integration circuit 83 becomes constant. On the other hand, the digital / analog converter (86) produces a constant analog signal according to the initial value data produced by an initial value generating circuit 85. As a result, the level of an analog output signal produced from an addition circuit 87 is kept constant. Consequently, also in the display device according to example 4 or 5, if the scanning frequency varies, the level of the convergence correction signal can be kept constant until the secured phase cycle circuit 3 is restored and the system clock stabilizes, and it becomes possible to avoid a clutter in the image display. Example 7 In this example a device is described ^ • a »- - ... ^^ i ^^^. ,,. . ^ • dU ^ and l ^ kj ^ fi ^. ** e3te * &:. display capable of avoiding any disorder in the displayed image due to sudden variation in the convergence correction signal on the upper edge and on the lower edge of the screen browser in the underexploration state. Figure 31 is a diagram showing an example of an essential part of a display device according to this example 7, and is a block diagram showing another example of a configuration of the digital convergence correction device B3 shown in FIG. Figure 25. This convergence correction device comprises the convergence correction device shown in Figure 29 to which is added an address control circuit 19A different from that of Figure 29. Figures 32 and 33 are time graphs to explain an example of the operation of an address control circuit 19A shown in FIG. 31, and shows a variation in the case of subexploration. In these drawings, (a) indicates a vertical bleaching pulse V_BLK, (b) indicates a vertical display area detection signal V_DIS, (c) indicates a horizontal bleaching pulse H_BLK, (d) indicates a detection signal of horizontal display area H_DIS, and (e) indicates a convergence correction signal iCY which is a driving signal of the convergence core coil C2.

J »á«. - •; - ^ ° - "« "'--- jj ^? ^ Toi' The address control circuit 19A produces the same address to the address counter 5 for each horizontal scanning period, so that the same convergence correction over the entire horizontal scanning period from a first transition of the vertical bleed pulse V_BLK to a first transition of the vertical display area signal V_DIS. This address is an address produced first to the address counter 5 after the first transition of the vertical display area detection signal V_DIS. In accordance with the foregoing, each of the correction data read during the first horizontal scan period of the field is also read during each horizontal scan period after the first transition of the vertical display area detection signal V_DIS. Figure 32 shows the status at this time. There is no variation in the convergence correction signal between the states before and after the variation in the first transition of the vertical display area detection signal V_DIS, that is, in the comparison between the first period of horizontal exploration in the field and the previous period of horizontal exploration. In accordance with the foregoing, it is possible to avoid a disorder in the display image at the upper edge of the effective area of the image in the vicinity due to sudden variation in the convergence correction signal.

The address control circuit 19A produces the same direction to the address counter for each horizontal scanning period, so that the same convergence correction is made in every horizontal scanning period until the last transition of the detection area signal vertical display V_DIS and the first transition of vertical bleed impulse V_BLK. This address is an address produced finally to the address counter 5 before the last transition to the detection signal of the vertical display area V_DIS. In accordance with the foregoing, each of the correction data read during the first horizontal scan period of the field is also read during each horizontal scan period after the last transition of the detection signal of the vertical display area V_DIS. Figure 33 shows the status at this time. There is no variation in the convergence correction signal between the states before and after the variation in the last transition of the detection signal of the vertical display area V_DIS, that is, in the comparison between the first horizontal scan period of the field and the previous period of horizontal exploration. In accordance with the above, it is possible to avoid a disorder in the display image at the lower edge of the effective area of the image or in the neighborhood thereof due to sudden variation in the convergence correction signal. ^^ ^ ^ _ ^ Figure 34 is an explanatory view schematically showing this state on the screen. From the upper edge of the screen browser to the upper edge of the effective area of the image, and from the lower edge of the effective area of the image to the lower edge of the screen browser, the same and equal convergence correction is made in its directions respective verticals. Accordingly, the convergence correction signal does not vary at the upper edge and at the lower edge of the image display area in the underexploration state. As a result, it is possible to avoid clutter in the image due to sudden variation of the convergence correction signal. Although an example in which the convergence correction varies before and after the first transition of the vertical bleaching pulse is described in this example 7, it is also preferable that the convergence correction varies at another time, for example, before and after the last transition of the vertical bleaching impulse. Example 8 In this example, a display device capable of easily storing correction data in memory 6 is described. Figure 35 is a diagram showing an example of a configuration of the display according to the invention.

¡JtiM M ^ ^ with this example 8. This display device comprises the display device shown in Figure 25 to which are added the image display circuit A3 and a digital convergence correction circuit B4 5 different from those of Figure 25. A display area indication signal HV_CSL and a correction point indication pattern L_CSL produced from the convergence correction circuit B4 are input to the image display circuit A3. And the image display circuit A3 displays an image on a cathode ray tube (C) according to any of the image input signals, the display area indication signal HV_CSL or the correction point indication pattern L_CSL. Figure 36 is a block diagram showing a example of a configuration of a convergence correction device B4 shown in Figure 35. This convergence correction circuit B4 comprises the convergence correction circuit shown in Figure 31 to which a pattern generation circuit 21 is added. The circuit of pattern generation 21 generates a correction point indication pattern L_CSL having a predetermined width in horizontal direction synchronously with the system clock, according to the vertical display area detection signal V_DIS and the area detection signal display horizontal H_DIS. The position and width of each pattern is it can optionally be fixed by a microcomputer not shown. Figure 37 is a diagram showing an example of the correction point indication pattern L_CSL displayed on the screen by the image display circuit A3, together with the vertical display area detection signal V_DIS and the detection signal of horizontal display area H_DIS. It is necessary to obtain the correction data with respect to the entire effective area of the image in the state of over-exploration. That is, the display area shown in the drawing matches the effective area of the image. In this drawing, the effective area of the image is evenly divided into 5 x 5 = 25 points, and assuming that the upper left end is an origin (0, 0) of coordinates, the convergence correction points of 25 points are designated in order to the coordinates (4, 4) of the lower right end. Figure 38 is a diagram showing an example of an adjustment order with respect to each correction point of convergence of the 25 points shown in Figure 37. First, an operator who monitors the correction point designation pattern on the screen, makes a convergence amount adjustment, for example, in order of (0, 0)? (0, 1)? (0, 2)? (0, 3)? (0, 4)? (1, 0)? (2, 0)? (3.0)? (4, 0)? (1, 1)? (2, 1)? (3 ,1)? (4, 1)? (1, 2)? (2, 2)? (3, 2)? (4, 2)? (1, 3)? (2, 3)? (3, 3)? ( 4, 3)? J ^ tó ™ (1, 4)? (2, 4)? (3, 4)? (4, 4). In this way, an optimum convergence correction amount is obtained. The amount of convergence correction obtained is stored directly in the direction corresponding to the correction point of the convergence of the memory 6 as a correction data. Points other than these convergence correction points can be obtained by linear interpolation of the correction data at the mentioned convergence correction points. That is, an area surrounded by The adjacent 4-point convergence correction is divided into four equal parts. Then, for example, with respect to each convergence correction point located between the coordinates (0, 0) and the coordinates (0, 1), a convergence correction amount is obtained using the amount of convergence correction in the coordinates (0, 0) and in the coordinates (0, 1). Then, with respect to each convergence correction point located between the coordinates (0, 0) and the coordinates (1, 0), a convergence correction amount is obtained using the correction amount of convergence in the coordinates (0, 0) and in the coordinates (1, 0). At this time, even in the case of variation in the scanning frequency, effective image area (image size), etc., the vertical display area detection signal V_DIS and the area detection signal horizontal display H DIS coincide with the effective area ----- ** ** > '- - from image. Therefore, an optimum convergence correction amount can be obtained only by performing linear interpolation using a time as a variable and using a correlation between the position on a screen 5 of the vertical deflection current iDYV and the horizontal deflection current iDYH. In this way, as the interpolation operation is performed using the vertical deflection current iDYV and the horizontal deflection current iDYH corresponding to the image area as a time parameter, it is possible to ensure the precision in convergence correction without influence of the variation in the scan frequency and image size. Although in Figure 38 an example is shown in which the effective area of the image is evenly divided into 5 x 5 = 25 points, it is impossible to improve the accuracy in convergence correction plus increasing the designation pattern of correction point, for example, to 5 x 9 = 45 points or to 9 x 9 = 81 points. Example 9 This example describes a display device comprising a digital convergence correction device for storing and maintaining a convergence correction amount with respect to each convergence correction point as a correction data. He display device is able to perform a desired convergence correction even in the case of variation in the correspondence relationship between the screen browser and the effective area of the image. Figure 39 is a block diagram showing schematically an example of a configuration of the display device according to this example 9. This display device comprises the display device shown in Figure 35 to which the correction circuit is added. of digital convergence B5 different from 10 in Figure 35. Figure 40 is a block diagram showing an example of a configuration of a digital convergence correction device B5 shown in Figure 39. This convergence correction circuit comprises the convergence correction circuit 15 shown in Figure 36 to which is added a different memory section 6X, a digital / analog converter (8X) and a 9X low pass filter section, not including a one-bit latch and a latch circuit. gate impulse generation. The memory section 6 comprises the memories 60 to 6n corresponding to different frequencies, and the low pass filter section 9X comprises low pass filters 90 to 9n corresponding to different frequencies. The frequency detection circuit 12 produces a selection signal according to the horizontal bleaching pulse H_BLK and the & > .a, jfe. ~.? > fc_Z? ~ t? s? d Btot &A ~. .-xiL.f? A. .- «o» u "_ -asiasi. T _-_- R - ff? Fpiffl _-- íf? £ t.-_ AlÉ8_r ^ ^ ^ S «^ a ^ Jt8alÍa__ll __-... vertical bleed pulse V_BLK, selects a memory 6i of those forming the 6X memory section, and selects a low pass filter 9i of those forming the 9X low pass filter section. The digital / analog converter (8X) is a digital / analog converter circuit for converting the correction data into an analog signal, and comprises a digital / analog converter having a width of 8 bits if the width of the correction data It is 8 bits. According to the direction of the address counter 5, the correction data are read from the selected memory 6i synchronously with screen scanning, and the read correction data are converted into analog signal by the digital / analog converter (8X). This analog signal is smoothed, and an iDY convergence correction signal is generated by the low pass filter 9i corresponding to the scanning frequency of the input image signal. This convergence correction device comprises a display area detection circuit 17, a horizontal display area detection circuit 18, and an address control circuit 19A. As a result, in the same manner as in example 4, the address counter 5 generates an address corresponding to each convergence correction point located in the effective area of the image in the case of over-scanning. At case of under-scanning, a corresponding address is generated , U > ... ^ efe *, ... x., .. * & * _. gfa _ .-? tL * .... > ..... _Í__ - .. _ * _ »to each convergence correction point located in the screen browser. In accordance with the above, a convergence correction corresponding to the relationship between the screen browser and the effective area of the image can be performed at all times. On the other hand, in the case of variation in the scanning frequency, it is possible to deal with the variation by selecting the memory 6i corresponding to the scanning frequency and the low-pass filter 9i corresponding to the scanning frequency. As a result, even if the relationship between the screen browser and the effective area of the image varies due to the variation in the scanning frequency, it is possible to perform a desired convergence correction. further, not only in the case of variation in the relationship between the screen browser and the effective area of the image due to the variation in scanning frequency but also in the case of the same scanning frequency, it is possible to perform a convergence correction desired when the relationship between the screen browser and the effective area of the image is different. In the same manner as in example 5, by providing an indication signal generation circuit 21, it is possible to produce a display area indication signal HV CSL in accordance with the detection signal of s & ^^^^^ ^^^^ & ^^^^^^ H13 & ia ± vertical display area V_DIS and the horizontal display area detection signal H_DIS. As a result, it is possible to display a rectangular frame image showing a peripheral edge portion of the display area on the screen and easily obtain data from the vertical effective image area signal V_DIS0 and data from the horizontal effective image area signal H_DIS0. Furthermore, in the same manner as in example 7, by providing the address control circuit 19A, in the case of sub-scanning, it is possible to avoid a disorder when displaying image caused by the sudden variation in the convergence correction signal on the edge top and bottom edge of the screen browser. -vasafe-

Claims (20)

1. CLAIMS 1. A digital convergence correction device comprising: a memory for storing correction data for each convergence correction point corresponding to a position on the screen in a one-to-one ratio, and an address counter for generating a direction of reading with respect to memory synchronously with screen scanning; and in which a convergence correction signal is generated according to the correction data read; characterized in that said digital convergence correction device comprises: a vertical display area detection circuit for generating and producing a vertical display area detection signal corresponding to a position in the vertical direction of an image display area on the screen according to a current of vertical deflection; and an address control circuit for controlling an address counter according to the vertical display area detection signal.
2. 2. The digital convergence correction device according to claim 1, characterized in that the display area detection circuit vertical comprises a comparator for comparing a current value of the vertical deflection current with a predetermined comparison level, and in the case of subexploration, a level corresponding to positions of two extremes in the vertical direction of a screen browser is used as a level of comparison, and in the case of over-scanning, a level corresponding to positions of two ends in the vertical direction of an effective image area is used as a comparison level.
3. 3. The digital convergence correction device according to claim 2, characterized in that the address circuit preliminarily stores the vertical display area detection signal in the case of over-scanning as an image vertical effective area signal, and in the case of subexploration, a time delay is obtained between a timing of the variation in the vertical effective area image signal and a timing of variation in the vertical display area detection signal, and the time delay is converts to a read address and occurs for the address counter.
4. 4. The digital convergence correction circuit according to claim 1, characterized in that it comprises a signal generation signal circuit to produce an indication signal for the area of ** a ~ * - *? ^ t display indicating an image display area in a vertical direction on the screen according to the vertical display area detection signal. A display device characterized in that it comprises the digital convergence correction device according to claim 4, and an image display circuit for displaying an image in accordance with the display area indication signal of the correction circuit of digital convergence The digital convergence correction device according to claim 1, characterized in that in the case of over-scanning, the address control circuit produces a read direction during a first horizontal scan period to the address counter for each horizontal scanning period, from a variation time in the vertical synchronization signal to a variation time in the detection signal of the vertical display area, according to the vertical synchronization signal and the vertical display area detection signal . The digital convergence correction device according to claim 1, characterized in that in the case of over-scanning, the address control circuit produces a reading direction during a # *** final horizontal scan period to the address counter for each horizontal scan period, from a time of variation in the vertical synchronization signal to a time of variation in the detection signal of display area 5, according to the vertical synchronization signal and the detection signal of the vertical display area. 8. A display device characterized in that it comprises the digital convergence correction device according to any of claims 1 to 3, 6 and 7. 9. A digital convergence correction device comprising: a memory for storing data of correction for each convergence correction point that corresponds to a position on a screen in a one-to-one ratio, and an address counter to generate a read address with respect to memory synchronously with screen scanning; and in which a convergence correction signal is generated according to the correction data read; characterized in that the digital convergence correction device comprises: a horizontal display area detection circuit for generating and producing a corresponding horizontal display area detection signal ^^^^^^^^^^^ ^ ^ ^ gj ^ tL * ^ ** B? í a? ¡? et.u- .. to a position in the horizontal direction of an image display area on the screen according to a horizontal deflection current; and an address control circuit for controlling an address counter according to the horizontal display area detection signal. The digital convergence correction device according to claim 9, characterized in that the horizontal display area detection circuit comprises a comparator for comparing a current value of the horizontal deviation current with a predetermined comparison level, and in the case of subexploration, a level that corresponds to positions of two extremes in the horizontal direction of the screen browser is used as a level of comparison; and in the case of over-scanning, a level corresponding to positions of two ends in the horizontal direction of the effective image area is used as a comparison level. The digital convergence correction device according to claim 9, characterized in that the address circuit preliminarily stores the horizontal display area detection signal in the case of over-scanning as a horizontal effective area signal of the image , and in the case of subexploration, it jjf tfitf? - - r ^^^: ^ ^ .. * .. ^ am * 6? l? tU ». obtains a time delay between a timing of variation in the horizontal effective image area signal and a timing of variation in the horizontal display area detection signal, and the time delay becomes a read and produced address to the counter of directions. 12. A display device characterized in that it comprises the digital convergence correction device according to any of claims 9 to 11. 13. The digital convergence correction circuit according to claim 9, characterized in that it comprises a indication signal generation circuit for producing a display area indication signal indicating an image display area in the horizontal direction on the screen according to the horizontal display area detection signal. 14. A display device characterized by uu comprises the digital convergence correction device according to claim 13, and an image display circuit for displaying an image in accordance with the display area indication signal from the digital convergence correction. 15. A convergence correction device * * * * * - A "* ^ ¡¡ü? * *" «'84 digital comprising: a memory to store correction data for each point of convergence correction corresponding to a position on a screen in a one-to-one ratio, and an address counter to generate a read address with respect to the memory synchronously with screen scanning, and in which a convergence correction signal is generated according to the correction data read , characterized in that the digital convergence 10 comprises: a vertical display area detection circuit for generating and producing a vertical display area detection signal corresponding to a position in the vertical direction of the image display area 15 on the screen according to a vertical deflection current, a horizontal display area detection circuit for generating and producing a detection signal horizontal display that corresponds to a position in the horizontal direction of an image display area on the screen according to a horizontal deflection current; and an address control circuit for controlling an address counter according to the vertical display area detection signal. 16. The digital convergence correction device according to claim 15, characterized in that the vertical display area detection circuit comprises a comparator for comparing a current value 5 of the vertical deflection current with a predetermined comparison level, and in the In the case of underexploration, a level that corresponds to two-end positions in the vertical direction of the screen browser is used as a level of comparison, and in the case of over-exploration, a The level corresponding to two-end positions in the vertical direction of the effective area of the image is used as a level of comparison; and the horizontal display area detection circuit comprises a comparator to compare 15 a current value of the horizontal deflection current with a predetermined comparison level, and in the case of subexploration, a level corresponding to two-way positions in the horizontal direction of the screen browser is used as a comparison level, and in In the case of over-scan, a level corresponding to positions of two extremes in the horizontal direction of the effective area of the image is used as a level of comparison. 17. The digital convergence correction device according to claim 15, characterized 25 poruq the address circuit preliminarily stores the ¿^^^^ ¿¿¿¿¿¿¿¿^ ^^^^^^^^ - - detection signal of vertical display area in the case of over-scanning as a vertical effective area signal of the image and the address circuit preliminarily stores the horizontal display area detection signal 5 in the case of over-scanning as a horizontal effective image area signal, - and in the case of under-scanning, a time delay between a variation timing in the vertical effective area signal of the image and a timing of variation 10 in the vertical display area detection signal is obtained and a time delay between a timing of variation in the horizontal effective image area signal and a timing of variation in the horizontal display area detection signal is obtained, - and the delays 15 convert to a read address and are produced for the address counter. 18. A display device characterized in that it comprises the digital convergence correction device according to any of the claims of the 20 to 17. The digital convergence correction circuit according to claim 15, characterized in that it comprises a signal generation signal circuit to produce a signal indicating area of 25 display indicating an image display area in the vertical direction on the screen according to the detection signal of the vertical display area and the detection signal of the horizontal display area. 20. A display device characterized in that it comprises the digital convergence correction device according to claim 19, and an image display circuit for displaying an image according to the display area indication signal from the correction circuit. of digital convergence. t * ^^. . ^ ^ ^ M ^. ._ «. ^^ ^