MX9802611A - Sistema procesador de datos y metodo para completar instrucciones con orden alterado. - Google Patents

Sistema procesador de datos y metodo para completar instrucciones con orden alterado.

Info

Publication number
MX9802611A
MX9802611A MX9802611A MX9802611A MX9802611A MX 9802611 A MX9802611 A MX 9802611A MX 9802611 A MX9802611 A MX 9802611A MX 9802611 A MX9802611 A MX 9802611A MX 9802611 A MX9802611 A MX 9802611A
Authority
MX
Mexico
Prior art keywords
interruptible
data processing
processing system
speculative
instruction
Prior art date
Application number
MX9802611A
Other languages
English (en)
Inventor
Hoichi Cheong
Paul Joseph Jordan
Hung Qui Le
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX9802611A publication Critical patent/MX9802611A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Durante la operacion de un sistema procesador de datos canalizado, una tabla de instrucciones interrumpibles se usa para almacenar identificadores de objetivos asociados con instrucciones las cuales pueden resultar en una ejecucion especulativa. Durante la operacion de la tabla de instrucciones interrumpible, un indicador, mencionado como un indicador de entrada de memoria temporal de terminacion de instrucciones, señala a un fondo de la tabla de instrucciones interrumpible si esa tabla incluye alguna instruccion. Una entrada en el fondo de la tabla de instrucciones interrumpible es una siguiente instruccion por completar. Esta entrada incluye un identificador de objetivo, nombrado como la TID no especulativa y no interrumpible, se puede usar para liberar fuentes mantenidas para todas las instrucciones ejecutadas anteriormente. El sistema procesador de datos determina el valor de la TID no especulativa y no interrumpible, para asegurar que se conserve una determinacion de orden y suministre un punto de ejecucion especulativa verdadera.
MX9802611A 1997-04-25 1998-04-03 Sistema procesador de datos y metodo para completar instrucciones con orden alterado. MX9802611A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/840,919 US5875326A (en) 1997-04-25 1997-04-25 Data processing system and method for completing out-of-order instructions

Publications (1)

Publication Number Publication Date
MX9802611A true MX9802611A (es) 1998-11-29

Family

ID=25283577

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9802611A MX9802611A (es) 1997-04-25 1998-04-03 Sistema procesador de datos y metodo para completar instrucciones con orden alterado.

Country Status (5)

Country Link
US (1) US5875326A (es)
KR (1) KR19980079722A (es)
BR (1) BR9801432A (es)
MX (1) MX9802611A (es)
SG (1) SG66457A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6085263A (en) * 1997-10-24 2000-07-04 Compaq Computer Corp. Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
US5974524A (en) * 1997-10-28 1999-10-26 International Business Machines Corporation Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution
US6134645A (en) * 1998-06-01 2000-10-17 International Business Machines Corporation Instruction completion logic distributed among execution units for improving completion efficiency
SE9902373D0 (sv) * 1998-11-16 1999-06-22 Ericsson Telefon Ab L M A processing system and method
SE9901146D0 (sv) 1998-11-16 1999-03-29 Ericsson Telefon Ab L M A processing system and method
SE9901145D0 (sv) 1998-11-16 1999-03-29 Ericsson Telefon Ab L M A processing system and method
US6543002B1 (en) * 1999-11-04 2003-04-01 International Business Machines Corporation Recovery from hang condition in a microprocessor
US7467325B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Processor instruction retry recovery
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US9672045B2 (en) 2014-09-30 2017-06-06 International Business Machines Corporation Checkpoints for a simultaneous multithreading processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0122528B1 (ko) * 1993-01-08 1997-11-20 윌리엄 티.엘리스 슈퍼스칼라 프로세서 시스템에서 중간 기억 버퍼의 할당을 인덱스하기 위한 방법 및 시스템
US5590351A (en) * 1994-01-21 1996-12-31 Advanced Micro Devices, Inc. Superscalar execution unit for sequential instruction pointer updates and segment limit checks
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions
TW260765B (es) * 1994-03-31 1995-10-21 Ibm
US5708788A (en) * 1995-03-03 1998-01-13 Fujitsu, Ltd. Method for adjusting fetch program counter in response to the number of instructions fetched and issued

Also Published As

Publication number Publication date
US5875326A (en) 1999-02-23
BR9801432A (pt) 1999-06-01
KR19980079722A (ko) 1998-11-25
SG66457A1 (en) 1999-07-20

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Legal Events

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