MX9603373A - Metodo y sistema para la acumulacion de valores en un dispositivo de computacion. - Google Patents

Metodo y sistema para la acumulacion de valores en un dispositivo de computacion.

Info

Publication number
MX9603373A
MX9603373A MX9603373A MX9603373A MX9603373A MX 9603373 A MX9603373 A MX 9603373A MX 9603373 A MX9603373 A MX 9603373A MX 9603373 A MX9603373 A MX 9603373A MX 9603373 A MX9603373 A MX 9603373A
Authority
MX
Mexico
Prior art keywords
computing device
processing elements
accumulation
accumulating values
outputs
Prior art date
Application number
MX9603373A
Other languages
English (en)
Inventor
Scott Edward Lloyd
Shay-Ping Thomas Wang
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of MX9603373A publication Critical patent/MX9603373A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

Se describe un método y sistema que permite la sobreposicion de ejecucion en una computadora que tiene una pluralidad de elementos de procesamiento (82), (84), (86). El método y sistema proporciona un cuadro de acumulacion en base a los tiempos de término esperados de los elementos de procesamiento (82), (84), (86) se acumulan de acuerdo al cuadro de acumulacion. El cuadro de acumulacion incluye una pluralidad de indicadores de acumulacion que indican cuando están por acumularse las salidas.
MX9603373A 1994-12-14 1995-10-10 Metodo y sistema para la acumulacion de valores en un dispositivo de computacion. MX9603373A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/355,738 US5664192A (en) 1994-12-14 1994-12-14 Method and system for accumulating values in a computing device
PCT/US1995/013559 WO1996018955A1 (en) 1994-12-14 1995-10-10 Method and system for accumulating values in a computing device

Publications (1)

Publication Number Publication Date
MX9603373A true MX9603373A (es) 1997-03-29

Family

ID=23398644

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9603373A MX9603373A (es) 1994-12-14 1995-10-10 Metodo y sistema para la acumulacion de valores en un dispositivo de computacion.

Country Status (6)

Country Link
US (1) US5664192A (es)
CN (1) CN1140497A (es)
AU (1) AU3964295A (es)
CA (1) CA2182594A1 (es)
MX (1) MX9603373A (es)
WO (1) WO1996018955A1 (es)

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US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8244789B1 (en) 2008-03-14 2012-08-14 Altera Corporation Normalization of floating point operations in a programmable integrated circuit device
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US8255448B1 (en) 2008-10-02 2012-08-28 Altera Corporation Implementing division in a programmable integrated circuit device
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US8549055B2 (en) 2009-03-03 2013-10-01 Altera Corporation Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
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US8886696B1 (en) 2009-03-03 2014-11-11 Altera Corporation Digital signal processing circuitry with redundancy and ability to support larger multipliers
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8805916B2 (en) 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8458243B1 (en) 2010-03-03 2013-06-04 Altera Corporation Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9379687B1 (en) 2014-01-14 2016-06-28 Altera Corporation Pipelined systolic finite impulse response filter
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
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Also Published As

Publication number Publication date
US5664192A (en) 1997-09-02
WO1996018955A1 (en) 1996-06-20
CA2182594A1 (en) 1996-06-20
CN1140497A (zh) 1997-01-15
AU3964295A (en) 1996-07-03

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