DE3686741D1 - Verfahren und rechneranordnung fuer die bedingte datenverarbeitung. - Google Patents
Verfahren und rechneranordnung fuer die bedingte datenverarbeitung.Info
- Publication number
- DE3686741D1 DE3686741D1 DE8686108416T DE3686741T DE3686741D1 DE 3686741 D1 DE3686741 D1 DE 3686741D1 DE 8686108416 T DE8686108416 T DE 8686108416T DE 3686741 T DE3686741 T DE 3686741T DE 3686741 D1 DE3686741 D1 DE 3686741D1
- Authority
- DE
- Germany
- Prior art keywords
- data processing
- computer arrangement
- conditional data
- conditional
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/750,809 US4747046A (en) | 1985-06-28 | 1985-06-28 | Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3686741D1 true DE3686741D1 (de) | 1992-10-22 |
DE3686741T2 DE3686741T2 (de) | 1993-01-21 |
Family
ID=25019253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686108416T Expired - Fee Related DE3686741T2 (de) | 1985-06-28 | 1986-06-20 | Verfahren und rechneranordnung fuer die bedingte datenverarbeitung. |
Country Status (6)
Country | Link |
---|---|
US (2) | US4747046A (de) |
EP (1) | EP0206276B1 (de) |
JP (1) | JPH0769795B2 (de) |
AU (1) | AU583929B2 (de) |
CA (1) | CA1258712A (de) |
DE (1) | DE3686741T2 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4814976C1 (en) * | 1986-12-23 | 2002-06-04 | Mips Tech Inc | Risc computer with unaligned reference handling and method for the same |
CA1327080C (en) * | 1987-05-26 | 1994-02-15 | Yoshiko Yamaguchi | Reduced instruction set computer (risc) type microprocessor |
JPH0330018A (ja) * | 1989-06-28 | 1991-02-08 | Nec Corp | 10進演算方式 |
JP2655191B2 (ja) * | 1989-07-05 | 1997-09-17 | 三菱電機株式会社 | 演算処理装置 |
CA2045735A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Computer performance by eliminating branches |
WO1994029790A1 (en) * | 1993-06-14 | 1994-12-22 | Apple Computer, Inc. | Method and apparatus for finding a termination character within a variable length character string or a processor |
US5815695A (en) * | 1993-10-28 | 1998-09-29 | Apple Computer, Inc. | Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor |
US6026484A (en) * | 1993-11-30 | 2000-02-15 | Texas Instruments Incorporated | Data processing apparatus, system and method for if, then, else operation using write priority |
US6058473A (en) * | 1993-11-30 | 2000-05-02 | Texas Instruments Incorporated | Memory store from a register pair conditional upon a selected status bit |
DE4430195B4 (de) * | 1993-12-13 | 2004-09-23 | Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto | Verfahren zur Auswertung von Booleschen Ausdrücken |
US5623615A (en) * | 1994-08-04 | 1997-04-22 | International Business Machines Corporation | Circuit and method for reducing prefetch cycles on microprocessors |
US5768172A (en) * | 1995-10-04 | 1998-06-16 | Apple Computer, Inc. | Graphic software functions without branch instructions |
US7801215B2 (en) * | 2001-07-24 | 2010-09-21 | Sasken Communication Technologies Limited | Motion estimation technique for digital video encoding applications |
JP3851228B2 (ja) | 2002-06-14 | 2006-11-29 | 松下電器産業株式会社 | プロセッサ、プログラム変換装置及びプログラム変換方法、並びにコンピュータプログラム |
EP1387255B1 (de) * | 2002-07-31 | 2020-04-08 | Texas Instruments Incorporated | Test- und Übersprungbefel mit mindestens einem Registeroperand |
EP1387254B1 (de) * | 2002-07-31 | 2012-12-12 | Texas Instruments Incorporated | Übersprungbefehl, der einen Test mit direkten Daten durchführt |
EP1891517A4 (de) | 2005-05-24 | 2008-08-13 | Texas Instruments Inc | Operand mit anzeige zur verarbeitung von mikrosequenzen |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3577190A (en) * | 1968-06-26 | 1971-05-04 | Ibm | Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions, in response to the occurrence of certain conditions |
US3881173A (en) * | 1973-05-14 | 1975-04-29 | Amdahl Corp | Condition code determination and data processing |
EP0072373B1 (de) * | 1981-08-19 | 1986-03-19 | International Business Machines Corporation | Mikroprozessor |
US4569016A (en) * | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
US4589065A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system |
US4618956A (en) * | 1983-09-29 | 1986-10-21 | Tandem Computers Incorporated | Method of operating enhanced alu test hardware |
US4654786A (en) * | 1984-04-11 | 1987-03-31 | Texas Instruments Incorporated | Data processor using picosquencer to control execution of multi-instruction subroutines in a single fetch cycle |
-
1985
- 1985-06-28 US US06/750,809 patent/US4747046A/en not_active Expired - Lifetime
-
1986
- 1986-06-13 CA CA000511576A patent/CA1258712A/en not_active Expired
- 1986-06-20 EP EP86108416A patent/EP0206276B1/de not_active Expired
- 1986-06-20 DE DE8686108416T patent/DE3686741T2/de not_active Expired - Fee Related
- 1986-06-23 JP JP61146759A patent/JPH0769795B2/ja not_active Expired - Lifetime
- 1986-06-27 AU AU59341/86A patent/AU583929B2/en not_active Ceased
-
1987
- 1987-12-30 US US07/139,508 patent/US4873627A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4873627A (en) | 1989-10-10 |
AU583929B2 (en) | 1989-05-11 |
AU5934186A (en) | 1987-01-08 |
US4747046A (en) | 1988-05-24 |
EP0206276A2 (de) | 1986-12-30 |
DE3686741T2 (de) | 1993-01-21 |
EP0206276A3 (en) | 1988-10-05 |
JPS623335A (ja) | 1987-01-09 |
JPH0769795B2 (ja) | 1995-07-31 |
CA1258712A (en) | 1989-08-22 |
EP0206276B1 (de) | 1992-09-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), |
|
8339 | Ceased/non-payment of the annual fee |