MX2022001501A - Acelerador de hardware basado en tensores que incluye una unidad de procesamiento escalar. - Google Patents
Acelerador de hardware basado en tensores que incluye una unidad de procesamiento escalar.Info
- Publication number
- MX2022001501A MX2022001501A MX2022001501A MX2022001501A MX2022001501A MX 2022001501 A MX2022001501 A MX 2022001501A MX 2022001501 A MX2022001501 A MX 2022001501A MX 2022001501 A MX2022001501 A MX 2022001501A MX 2022001501 A MX2022001501 A MX 2022001501A
- Authority
- MX
- Mexico
- Prior art keywords
- tensor
- scalar
- vectors
- hardware accelerator
- operations
- Prior art date
Links
- 239000013598 vector Substances 0.000 abstract 5
- 238000013528 artificial neural network Methods 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8061—Details on data memory access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
- G06F9/3881—Arrangements for communication of instructions and data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/047—Probabilistic or stochastic networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Biophysics (AREA)
- General Health & Medical Sciences (AREA)
- Artificial Intelligence (AREA)
- Life Sciences & Earth Sciences (AREA)
- Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Biomedical Technology (AREA)
- Molecular Biology (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Probability & Statistics with Applications (AREA)
- Advance Control (AREA)
- Auxiliary Drives, Propulsion Controls, And Safety Devices (AREA)
Abstract
En el presente documento se describe un sistema de cómputo que acelera las operaciones de redes neuronales profundas (DNN) u otras operaciones de procesamiento utilizando un acelerador de hardware. El acelerador de hardware, a su vez, incluye un motor de procesamiento tensorial que funciona en conjunto con una unidad de procesamiento escalar (SPU). El motor de procesamiento tensorial maneja varios tipos de operaciones basadas en tensores requeridas por la DNN, como multiplicar vectores por matrices, combinar vectores con otros vectores, transformar vectores individuales, etcétera. La SPU realiza operaciones basadas en escalares, como formar el recíproco de un escalar, generar la raíz cuadrada de un escalar, etcétera. De acuerdo con una implementación ilustrativa, el sistema de cómputo utiliza la misma interfaz programática basada en vectores para interactuar tanto con el motor de procesamiento tensorial como con la SPU.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/533,237 US10997116B2 (en) | 2019-08-06 | 2019-08-06 | Tensor-based hardware accelerator including a scalar-processing unit |
PCT/US2020/036873 WO2021025767A1 (en) | 2019-08-06 | 2020-06-10 | Tensor-based hardware accelerator including a scalar-processing unit |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2022001501A true MX2022001501A (es) | 2022-03-11 |
Family
ID=71899961
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2022001501A MX2022001501A (es) | 2019-08-06 | 2020-06-10 | Acelerador de hardware basado en tensores que incluye una unidad de procesamiento escalar. |
Country Status (6)
Country | Link |
---|---|
US (1) | US10997116B2 (es) |
EP (1) | EP4010794A1 (es) |
CN (1) | CN114207579A (es) |
CA (1) | CA3146416A1 (es) |
MX (1) | MX2022001501A (es) |
WO (1) | WO2021025767A1 (es) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11481604B2 (en) * | 2019-10-24 | 2022-10-25 | Alibaba Group Holding Limited | Apparatus and method for neural network processing |
US11455144B1 (en) * | 2019-11-21 | 2022-09-27 | Xilinx, Inc. | Softmax calculation and architecture using a modified coordinate rotation digital computer (CORDIC) approach |
US11734214B2 (en) * | 2021-02-01 | 2023-08-22 | Microsoft Technology Licensing, Llc | Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity |
EP4285286A1 (en) * | 2021-02-01 | 2023-12-06 | Microsoft Technology Licensing, LLC | Semi-programmable and reconfigurable co-accelerator for a deep neural network with normalization or non-linearity |
GB2608986B (en) * | 2021-06-28 | 2024-01-24 | Imagination Tech Ltd | Implementation of Argmax or Argmin in hardware |
EP4120142A1 (en) * | 2021-06-28 | 2023-01-18 | Imagination Technologies Limited | Implementation of argmax or argmin in hardware |
GB2608591B (en) * | 2021-06-28 | 2024-01-24 | Imagination Tech Ltd | Implementation of pooling and unpooling or reverse pooling in hardware |
US20240004647A1 (en) * | 2022-07-01 | 2024-01-04 | Andes Technology Corporation | Vector processor with vector and element reduction method |
KR20240007495A (ko) * | 2022-07-08 | 2024-01-16 | 리벨리온 주식회사 | 뉴럴 코어, 이를 포함하는 뉴럴 프로세싱 장치 및 뉴럴 프로세싱 장치의 데이터 로드 방법 |
CN116029332B (zh) * | 2023-02-22 | 2023-08-22 | 南京大学 | 一种基于lstm网络的片上微调方法及装置 |
Family Cites Families (20)
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JPH04336378A (ja) * | 1991-05-14 | 1992-11-24 | Nec Corp | 情報処理装置 |
GB2382887B (en) * | 2001-10-31 | 2005-09-28 | Alphamosaic Ltd | Instruction execution in a processor |
GB2390700B (en) | 2002-04-15 | 2006-03-15 | Alphamosaic Ltd | Narrow/wide cache |
US7146486B1 (en) * | 2003-01-29 | 2006-12-05 | S3 Graphics Co., Ltd. | SIMD processor with scalar arithmetic logic units |
US9367462B2 (en) * | 2009-12-29 | 2016-06-14 | Empire Technology Development Llc | Shared memories for energy efficient multi-core processors |
US20150067273A1 (en) | 2013-08-30 | 2015-03-05 | Microsoft Corporation | Computation hardware with high-bandwidth memory interface |
US9367519B2 (en) | 2013-08-30 | 2016-06-14 | Microsoft Technology Licensing, Llc | Sparse matrix data structure |
US20160125263A1 (en) | 2014-11-03 | 2016-05-05 | Texas Instruments Incorporated | Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor |
CN111651203B (zh) * | 2016-04-26 | 2024-05-07 | 中科寒武纪科技股份有限公司 | 一种用于执行向量四则运算的装置和方法 |
CN107315715B (zh) * | 2016-04-26 | 2020-11-03 | 中科寒武纪科技股份有限公司 | 一种用于执行矩阵加/减运算的装置和方法 |
US11055063B2 (en) * | 2016-05-02 | 2021-07-06 | Marvell Asia Pte, Ltd. | Systems and methods for deep learning processor |
EP3563307B1 (en) * | 2017-02-23 | 2023-04-12 | Cerebras Systems Inc. | Accelerated deep learning |
US10108581B1 (en) * | 2017-04-03 | 2018-10-23 | Google Llc | Vector reduction processor |
EP4361832A3 (en) * | 2017-05-17 | 2024-08-07 | Google LLC | Special purpose neural network training chip |
US10331445B2 (en) | 2017-05-24 | 2019-06-25 | Microsoft Technology Licensing, Llc | Multifunction vector processor circuits |
US10467324B2 (en) | 2017-05-24 | 2019-11-05 | Microsoft Technology Licensing, Llc | Data packing techniques for hard-wired multiplier circuits |
US10372456B2 (en) | 2017-05-24 | 2019-08-06 | Microsoft Technology Licensing, Llc | Tensor processor instruction set architecture |
US10338925B2 (en) | 2017-05-24 | 2019-07-02 | Microsoft Technology Licensing, Llc | Tensor register files |
JP2019057249A (ja) | 2017-09-22 | 2019-04-11 | 富士通株式会社 | 演算処理装置および演算処理方法 |
US11372804B2 (en) * | 2018-05-16 | 2022-06-28 | Qualcomm Incorporated | System and method of loading and replication of sub-vector values |
-
2019
- 2019-08-06 US US16/533,237 patent/US10997116B2/en active Active
-
2020
- 2020-06-10 MX MX2022001501A patent/MX2022001501A/es unknown
- 2020-06-10 WO PCT/US2020/036873 patent/WO2021025767A1/en unknown
- 2020-06-10 CN CN202080055428.XA patent/CN114207579A/zh active Pending
- 2020-06-10 EP EP20750542.1A patent/EP4010794A1/en active Pending
- 2020-06-10 CA CA3146416A patent/CA3146416A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20210042260A1 (en) | 2021-02-11 |
US10997116B2 (en) | 2021-05-04 |
WO2021025767A1 (en) | 2021-02-11 |
EP4010794A1 (en) | 2022-06-15 |
CN114207579A (zh) | 2022-03-18 |
CA3146416A1 (en) | 2021-02-11 |
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