MX2021005804A - Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion. - Google Patents
Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion.Info
- Publication number
- MX2021005804A MX2021005804A MX2021005804A MX2021005804A MX2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A
- Authority
- MX
- Mexico
- Prior art keywords
- memory
- computing device
- host computing
- virtual
- slat
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45579—I/O management, e.g. providing access to device drivers or storage
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45583—Memory management, e.g. access or allocation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1052—Security improvement
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/15—Use in a specific computing environment
- G06F2212/151—Emulated environment, e.g. virtual machine
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/50—Control mechanisms for virtual memory, cache or TLB
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/651—Multi-level translation tables
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/652—Page size control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/654—Look-ahead translation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/656—Address space sharing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/683—Invalidation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/198,620 US10901911B2 (en) | 2018-11-21 | 2018-11-21 | Faster computer memory access by reducing SLAT fragmentation |
| US16/423,137 US10761876B2 (en) | 2018-11-21 | 2019-05-27 | Faster access of virtual machine memory backed by a host computing device's virtual memory |
| PCT/US2019/061345 WO2020106533A1 (en) | 2018-11-21 | 2019-11-14 | Faster access of virtual machine memory backed by a host computing device's virtual memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MX2021005804A true MX2021005804A (es) | 2021-07-02 |
Family
ID=68841205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX2021005804A MX2021005804A (es) | 2018-11-21 | 2019-11-14 | Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion. |
Country Status (14)
| Country | Link |
|---|---|
| US (2) | US10761876B2 (enExample) |
| EP (2) | EP4418129A3 (enExample) |
| JP (1) | JP7592584B2 (enExample) |
| KR (1) | KR20210089150A (enExample) |
| CN (3) | CN120371735A (enExample) |
| AU (1) | AU2019384498A1 (enExample) |
| BR (1) | BR112021008419A2 (enExample) |
| CA (1) | CA3116380A1 (enExample) |
| IL (1) | IL283228B2 (enExample) |
| MX (1) | MX2021005804A (enExample) |
| PH (1) | PH12021551164A1 (enExample) |
| SG (1) | SG11202104744UA (enExample) |
| WO (1) | WO2020106533A1 (enExample) |
| ZA (1) | ZA202102321B (enExample) |
Families Citing this family (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021161104A1 (en) | 2020-02-12 | 2021-08-19 | Monday.Com | Enhanced display features in collaborative network systems, methods, and devices |
| WO2021220058A1 (en) | 2020-05-01 | 2021-11-04 | Monday.com Ltd. | Digital processing systems and methods for enhanced collaborative workflow and networking systems, methods, and devices |
| WO2021144656A1 (en) | 2020-01-15 | 2021-07-22 | Monday.Com | Digital processing systems and methods for graphical dynamic table gauges in collaborative work systems |
| US11410129B2 (en) | 2010-05-01 | 2022-08-09 | Monday.com Ltd. | Digital processing systems and methods for two-way syncing with third party applications in collaborative work systems |
| US11188651B2 (en) * | 2016-03-07 | 2021-11-30 | Crowdstrike, Inc. | Hypervisor-based interception of memory accesses |
| US12339979B2 (en) | 2016-03-07 | 2025-06-24 | Crowdstrike, Inc. | Hypervisor-based interception of memory and register accesses |
| US12248560B2 (en) | 2016-03-07 | 2025-03-11 | Crowdstrike, Inc. | Hypervisor-based redirection of system calls and interrupt-based task offloading |
| US11436359B2 (en) | 2018-07-04 | 2022-09-06 | Monday.com Ltd. | System and method for managing permissions of users for a single data type column-oriented data structure |
| US11698890B2 (en) | 2018-07-04 | 2023-07-11 | Monday.com Ltd. | System and method for generating a column-oriented data structure repository for columns of single data types |
| US12353419B2 (en) | 2018-07-23 | 2025-07-08 | Monday.com Ltd. | System and method for generating a tagged column-oriented data structure |
| US10901911B2 (en) | 2018-11-21 | 2021-01-26 | Microsoft Technology Licensing, Llc | Faster computer memory access by reducing SLAT fragmentation |
| EP4062313A1 (en) | 2019-11-18 | 2022-09-28 | Monday.com Ltd. | Collaborative networking systems, methods, and devices |
| US11829953B1 (en) | 2020-05-01 | 2023-11-28 | Monday.com Ltd. | Digital processing systems and methods for managing sprints using linked electronic boards |
| US11277361B2 (en) | 2020-05-03 | 2022-03-15 | Monday.com Ltd. | Digital processing systems and methods for variable hang-time for social layer messages in collaborative work systems |
| GB2595479B (en) * | 2020-05-27 | 2022-10-19 | Advanced Risc Mach Ltd | Apparatus and method |
| US12591444B2 (en) * | 2020-12-09 | 2026-03-31 | Mediatek Inc. | Hardware virtual machine for controlling access to physical memory space |
| WO2022153122A1 (en) | 2021-01-14 | 2022-07-21 | Monday.com Ltd. | Systems, methods, and devices for enhanced collaborative work documents |
| US11531452B2 (en) | 2021-01-14 | 2022-12-20 | Monday.com Ltd. | Digital processing systems and methods for group-based document edit tracking in collaborative work systems |
| US11455239B1 (en) * | 2021-07-02 | 2022-09-27 | Microsoft Technology Licensing, Llc | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system |
| US11586371B2 (en) * | 2021-07-23 | 2023-02-21 | Vmware, Inc. | Prepopulating page tables for memory of workloads during live migrations |
| US12105948B2 (en) | 2021-10-29 | 2024-10-01 | Monday.com Ltd. | Digital processing systems and methods for display navigation mini maps |
| US11860783B2 (en) | 2022-03-11 | 2024-01-02 | Microsoft Technology Licensing, Llc | Direct swap caching with noisy neighbor mitigation and dynamic address range assignment |
| WO2023239671A1 (en) * | 2022-06-06 | 2023-12-14 | Onnivation Llc | Virtual memory paging system and translation lookaside buffer with pagelets |
| US11853228B1 (en) | 2022-06-10 | 2023-12-26 | Arm Limited | Partial-address-translation-invalidation request |
| US12197329B2 (en) * | 2022-12-09 | 2025-01-14 | Advanced Micro Devices, Inc. | Range-based cache flushing |
| US11741071B1 (en) | 2022-12-28 | 2023-08-29 | Monday.com Ltd. | Digital processing systems and methods for navigating and viewing displayed content |
| US11886683B1 (en) | 2022-12-30 | 2024-01-30 | Monday.com Ltd | Digital processing systems and methods for presenting board graphics |
| US11893381B1 (en) | 2023-02-21 | 2024-02-06 | Monday.com Ltd | Digital processing systems and methods for reducing file bundle sizes |
| WO2024257014A1 (en) | 2023-06-13 | 2024-12-19 | Monday.com Ltd. | Digital processing systems and methods for enhanced data representation |
| CN117632010B (zh) * | 2023-11-23 | 2024-10-18 | 百代(上海)数据技术有限公司 | 快照任务处理系统以及快照任务执行方法 |
| WO2025114750A1 (en) | 2023-11-28 | 2025-06-05 | Monday.com Ltd. | Digital processing systems and methods for managing workflows |
| WO2025114749A1 (en) | 2023-11-28 | 2025-06-05 | Monday.com Ltd. | Digital processing systems and methods for facilitating the development and implementation of applications in conjunction with a serverless environment |
| US20260105006A1 (en) * | 2024-10-15 | 2026-04-16 | Microsoft Technology Licensing, Llc | Hybrid virtual machines having physically backed and virtually backed memory ranges |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8645665B1 (en) * | 2012-12-14 | 2014-02-04 | Intel Corporation | Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses |
| US7428626B2 (en) * | 2005-03-08 | 2008-09-23 | Microsoft Corporation | Method and system for a second level address translation in a virtual machine environment |
| US7653803B2 (en) | 2006-01-17 | 2010-01-26 | Globalfoundries Inc. | Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU) |
| US7917725B2 (en) | 2007-09-11 | 2011-03-29 | QNX Software Systems GmbH & Co., KG | Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer |
| US8352705B2 (en) | 2008-01-15 | 2013-01-08 | Vmware, Inc. | Large-page optimization in virtual memory paging systems |
| GB2478727B (en) | 2010-03-15 | 2013-07-17 | Advanced Risc Mach Ltd | Translation table control |
| US8364932B2 (en) | 2010-10-29 | 2013-01-29 | Vmware, Inc. | System and method to prioritize large memory page allocation in virtualized systems |
| US9336036B2 (en) * | 2011-03-31 | 2016-05-10 | Intel Corporation | System method for memory virtualization control logic for translating virtual memory in space of guest memory based on translated codes in response to memory failure |
| WO2014209269A1 (en) * | 2013-06-24 | 2014-12-31 | Intel Corporation | A protected memory view for nested page table access by virtual machine guests |
| US9202046B2 (en) * | 2014-03-03 | 2015-12-01 | Bitdefender IPR Management Ltd. | Systems and methods for executing arbitrary applications in secure environments |
| EP2955634B1 (en) * | 2014-06-10 | 2021-03-03 | Deutsche Telekom AG | Paravirtualization-based interface for memory management in virtual machines |
| US9501422B2 (en) | 2014-06-11 | 2016-11-22 | Vmware, Inc. | Identification of low-activity large memory pages |
| US9330015B2 (en) * | 2014-06-11 | 2016-05-03 | Vmware, Inc. | Identification of low-activity large memory pages |
| US9703726B2 (en) * | 2014-06-24 | 2017-07-11 | Bitdefender IPR Management Ltd. | Systems and methods for dynamically protecting a stack from below the operating system |
| US9792222B2 (en) * | 2014-06-27 | 2017-10-17 | Intel Corporation | Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure |
| US9703720B2 (en) * | 2014-12-23 | 2017-07-11 | Intel Corporation | Method and apparatus to allow secure guest access to extended page tables |
| US20160299712A1 (en) * | 2015-04-07 | 2016-10-13 | Microsoft Technology Licensing, Llc | Virtual Machines Backed by Host Virtual Memory |
| US20170123996A1 (en) * | 2015-11-02 | 2017-05-04 | Microsoft Technology Licensing, Llc | Direct Mapped Files in Virtual Address-Backed Virtual Machines |
| US10447728B1 (en) * | 2015-12-10 | 2019-10-15 | Fireeye, Inc. | Technique for protecting guest processes using a layered virtualization architecture |
-
2019
- 2019-05-27 US US16/423,137 patent/US10761876B2/en active Active
- 2019-11-14 IL IL283228A patent/IL283228B2/en unknown
- 2019-11-14 CN CN202510501453.0A patent/CN120371735A/zh active Pending
- 2019-11-14 CA CA3116380A patent/CA3116380A1/en active Pending
- 2019-11-14 KR KR1020217012320A patent/KR20210089150A/ko not_active Abandoned
- 2019-11-14 BR BR112021008419-3A patent/BR112021008419A2/pt not_active IP Right Cessation
- 2019-11-14 EP EP24186493.3A patent/EP4418129A3/en active Pending
- 2019-11-14 JP JP2021518693A patent/JP7592584B2/ja active Active
- 2019-11-14 CN CN202510501454.5A patent/CN120353730A/zh active Pending
- 2019-11-14 SG SG11202104744UA patent/SG11202104744UA/en unknown
- 2019-11-14 CN CN201980076709.0A patent/CN113168379B/zh active Active
- 2019-11-14 AU AU2019384498A patent/AU2019384498A1/en not_active Abandoned
- 2019-11-14 EP EP19817861.8A patent/EP3884392B1/en active Active
- 2019-11-14 MX MX2021005804A patent/MX2021005804A/es unknown
- 2019-11-14 WO PCT/US2019/061345 patent/WO2020106533A1/en not_active Ceased
-
2020
- 2020-08-30 US US17/006,858 patent/US11157306B2/en active Active
-
2021
- 2021-04-08 ZA ZA2021/02321A patent/ZA202102321B/en unknown
- 2021-05-21 PH PH12021551164A patent/PH12021551164A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN113168379B (zh) | 2025-05-06 |
| EP4418129A2 (en) | 2024-08-21 |
| ZA202102321B (en) | 2022-06-29 |
| US20200394065A1 (en) | 2020-12-17 |
| US10761876B2 (en) | 2020-09-01 |
| AU2019384498A1 (en) | 2021-05-13 |
| JP2022509906A (ja) | 2022-01-25 |
| IL283228A (en) | 2021-07-29 |
| US11157306B2 (en) | 2021-10-26 |
| CN120353730A (zh) | 2025-07-22 |
| PH12021551164A1 (en) | 2021-10-25 |
| EP3884392B1 (en) | 2024-07-17 |
| IL283228B1 (en) | 2023-12-01 |
| CA3116380A1 (en) | 2020-05-28 |
| US20200159558A1 (en) | 2020-05-21 |
| EP3884392A1 (en) | 2021-09-29 |
| WO2020106533A1 (en) | 2020-05-28 |
| CN120371735A (zh) | 2025-07-25 |
| KR20210089150A (ko) | 2021-07-15 |
| BR112021008419A2 (pt) | 2021-09-14 |
| SG11202104744UA (en) | 2021-06-29 |
| JP7592584B2 (ja) | 2024-12-02 |
| CN113168379A (zh) | 2021-07-23 |
| IL283228B2 (en) | 2024-04-01 |
| EP4418129A3 (en) | 2024-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| MX2021005804A (es) | Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion. | |
| US11620060B2 (en) | Unified hardware and software two-level memory | |
| US9904473B2 (en) | Memory and processor affinity in a deduplicated environment | |
| US8386749B2 (en) | Address mapping in virtualized processing system | |
| US10216642B2 (en) | Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size | |
| US9152570B2 (en) | System and method for supporting finer-grained copy-on-write page sizes | |
| KR100928353B1 (ko) | 가상 머신 환경에서의 주소 변환 지원 방법 및 장치 | |
| EP2812795B1 (en) | A method and apparatus for supporting address translation in a multiprocessor virtual machine environment using tracking data to eliminate interprocessor interrupts | |
| JP2017502435A5 (enExample) | ||
| US9092359B2 (en) | Identification and consolidation of page table entries | |
| MY156692A (en) | Translation table control | |
| EP4398138A3 (en) | Virtualization-based platform protection technology | |
| TW201411345A (zh) | 用於階層式記憶體系統之記憶體管理 | |
| JP2020524339A5 (enExample) | ||
| BR112019004916A2 (pt) | método e dispositivo para gravar dados armazenados no meio de armazenamento com base na memória flash | |
| BR112019001506A2 (pt) | atualização de endereços de memória virtual de funcionalidades de aplicação alvo para uma versão atualizada de código binário de aplicação | |
| US10565126B2 (en) | Method and apparatus for two-layer copy-on-write | |
| US10387325B2 (en) | Dynamic address translation for a virtual machine | |
| US20160259689A1 (en) | Managing reuse information in caches | |
| US20150154119A1 (en) | Memory allocation and page address translation system and method | |
| US10013360B2 (en) | Managing reuse information with multiple translation stages | |
| US20160275016A1 (en) | Managing address-independent page attributes | |
| EP3166019B1 (en) | Memory devices and methods | |
| CN104077176A (zh) | 增加虚拟机标识符域的方法及装置 | |
| US20190146693A1 (en) | Address space access control |