MX2021005804A - Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion. - Google Patents
Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion.Info
- Publication number
- MX2021005804A MX2021005804A MX2021005804A MX2021005804A MX2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A MX 2021005804 A MX2021005804 A MX 2021005804A
- Authority
- MX
- Mexico
- Prior art keywords
- memory
- computing device
- host computing
- virtual
- slat
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
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- G—PHYSICS
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G06F9/5077—Logical partitioning of resources; Management or configuration of virtualized resources
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
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- G—PHYSICS
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/15—Use in a specific computing environment
- G06F2212/151—Emulated environment, e.g. virtual machine
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/50—Control mechanisms for virtual memory, cache or TLB
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/651—Multi-level translation tables
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/652—Page size control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/654—Look-ahead translation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/656—Address space sharing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/683—Invalidation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Para aumentar la velocidad con la que se atraviesan los niveles jerárquicos de una tabla de direcciones de segunda capa (SLAT, por sus siglas en inglés) como parte de un acceso a la memoria en donde la memoria física del invitado de un entorno de la máquina virtual está respaldada por la memoria virtual asignada a uno o más procesos que se ejecutan en un dispositivo de cómputo anfitrión, uno o más niveles jerárquicos de las tablas dentro de la SLAT pueden omitirse o no hacerles referencia de otro modo. Si bien la SLAT puede completarse con correlaciones de memoria en niveles jerárquicamente más altos de las tablas, la tabla de paginación del dispositivo de cómputo anfitrión, que admite la provisión de memoria virtual del dispositivo de cómputo anfitrión, puede mantener un conjunto contiguo correspondiente de correlaciones de memoria en el nivel de tabla jerárquicamente más bajo, permitiendo así que el dispositivo de cómputo anfitrión pagine, o manipule de otro modo, fragmentos más pequeños de la memoria. Si ocurre tal manipulación, la SLAT puede completarse nuevamente con correlaciones de memoria al nivel de tabla jerárquicamente más bajo.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/198,620 US10901911B2 (en) | 2018-11-21 | 2018-11-21 | Faster computer memory access by reducing SLAT fragmentation |
US16/423,137 US10761876B2 (en) | 2018-11-21 | 2019-05-27 | Faster access of virtual machine memory backed by a host computing device's virtual memory |
PCT/US2019/061345 WO2020106533A1 (en) | 2018-11-21 | 2019-11-14 | Faster access of virtual machine memory backed by a host computing device's virtual memory |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2021005804A true MX2021005804A (es) | 2021-07-02 |
Family
ID=68841205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2021005804A MX2021005804A (es) | 2018-11-21 | 2019-11-14 | Acceso mas rapido de la memoria de la maquina virtual respaldado por la memoria virtual de un dispositivo de computo anfitrion. |
Country Status (14)
Country | Link |
---|---|
US (2) | US10761876B2 (es) |
EP (2) | EP4418129A3 (es) |
JP (1) | JP2022509906A (es) |
KR (1) | KR20210089150A (es) |
CN (1) | CN113168379A (es) |
AU (1) | AU2019384498A1 (es) |
BR (1) | BR112021008419A2 (es) |
CA (1) | CA3116380A1 (es) |
IL (1) | IL283228B2 (es) |
MX (1) | MX2021005804A (es) |
PH (1) | PH12021551164A1 (es) |
SG (1) | SG11202104744UA (es) |
WO (1) | WO2020106533A1 (es) |
ZA (1) | ZA202102321B (es) |
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WO2021144656A1 (en) | 2020-01-15 | 2021-07-22 | Monday.Com | Digital processing systems and methods for graphical dynamic table gauges in collaborative work systems |
US11410129B2 (en) | 2010-05-01 | 2022-08-09 | Monday.com Ltd. | Digital processing systems and methods for two-way syncing with third party applications in collaborative work systems |
WO2021161104A1 (en) | 2020-02-12 | 2021-08-19 | Monday.Com | Enhanced display features in collaborative network systems, methods, and devices |
US11188651B2 (en) * | 2016-03-07 | 2021-11-30 | Crowdstrike, Inc. | Hypervisor-based interception of memory accesses |
US11436359B2 (en) | 2018-07-04 | 2022-09-06 | Monday.com Ltd. | System and method for managing permissions of users for a single data type column-oriented data structure |
US11698890B2 (en) | 2018-07-04 | 2023-07-11 | Monday.com Ltd. | System and method for generating a column-oriented data structure repository for columns of single data types |
US11775890B2 (en) | 2019-11-18 | 2023-10-03 | Monday.Com | Digital processing systems and methods for map-based data organization in collaborative work systems |
EP4062313A1 (en) | 2019-11-18 | 2022-09-28 | Monday.com Ltd. | Collaborative networking systems, methods, and devices |
IL297858A (en) | 2020-05-01 | 2023-01-01 | Monday Com Ltd | Digital processing systems and methods for improved networking and collaborative work management systems, methods and devices |
US20240184989A1 (en) | 2020-05-01 | 2024-06-06 | Monday.com Ltd. | Digital processing systems and methods for virtualfile-based electronic white board in collaborative work systems systems |
US11277361B2 (en) | 2020-05-03 | 2022-03-15 | Monday.com Ltd. | Digital processing systems and methods for variable hang-time for social layer messages in collaborative work systems |
GB2595479B (en) * | 2020-05-27 | 2022-10-19 | Advanced Risc Mach Ltd | Apparatus and method |
US11397847B1 (en) | 2021-01-14 | 2022-07-26 | Monday.com Ltd. | Digital processing systems and methods for display pane scroll locking during collaborative document editing in collaborative work systems |
US11455239B1 (en) * | 2021-07-02 | 2022-09-27 | Microsoft Technology Licensing, Llc | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system |
US11586371B2 (en) * | 2021-07-23 | 2023-02-21 | Vmware, Inc. | Prepopulating page tables for memory of workloads during live migrations |
US12056664B2 (en) | 2021-08-17 | 2024-08-06 | Monday.com Ltd. | Digital processing systems and methods for external events trigger automatic text-based document alterations in collaborative work systems |
US12105948B2 (en) | 2021-10-29 | 2024-10-01 | Monday.com Ltd. | Digital processing systems and methods for display navigation mini maps |
US11860783B2 (en) | 2022-03-11 | 2024-01-02 | Microsoft Technology Licensing, Llc | Direct swap caching with noisy neighbor mitigation and dynamic address range assignment |
WO2023239671A1 (en) * | 2022-06-06 | 2023-12-14 | Onnivation Llc | Virtual memory paging system and translation lookaside buffer with pagelets |
US11853228B1 (en) * | 2022-06-10 | 2023-12-26 | Arm Limited | Partial-address-translation-invalidation request |
US11741071B1 (en) | 2022-12-28 | 2023-08-29 | Monday.com Ltd. | Digital processing systems and methods for navigating and viewing displayed content |
US11886683B1 (en) | 2022-12-30 | 2024-01-30 | Monday.com Ltd | Digital processing systems and methods for presenting board graphics |
US11893381B1 (en) | 2023-02-21 | 2024-02-06 | Monday.com Ltd | Digital processing systems and methods for reducing file bundle sizes |
US12056255B1 (en) | 2023-11-28 | 2024-08-06 | Monday.com Ltd. | Digital processing systems and methods for facilitating the development and implementation of applications in conjunction with a serverless environment |
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US8645665B1 (en) * | 2012-12-14 | 2014-02-04 | Intel Corporation | Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses |
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US9703720B2 (en) * | 2014-12-23 | 2017-07-11 | Intel Corporation | Method and apparatus to allow secure guest access to extended page tables |
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US20170123996A1 (en) * | 2015-11-02 | 2017-05-04 | Microsoft Technology Licensing, Llc | Direct Mapped Files in Virtual Address-Backed Virtual Machines |
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2019
- 2019-05-27 US US16/423,137 patent/US10761876B2/en active Active
- 2019-11-14 CN CN201980076709.0A patent/CN113168379A/zh active Pending
- 2019-11-14 CA CA3116380A patent/CA3116380A1/en active Pending
- 2019-11-14 IL IL283228A patent/IL283228B2/en unknown
- 2019-11-14 EP EP24186493.3A patent/EP4418129A3/en active Pending
- 2019-11-14 SG SG11202104744UA patent/SG11202104744UA/en unknown
- 2019-11-14 BR BR112021008419-3A patent/BR112021008419A2/pt unknown
- 2019-11-14 EP EP19817861.8A patent/EP3884392B1/en active Active
- 2019-11-14 WO PCT/US2019/061345 patent/WO2020106533A1/en unknown
- 2019-11-14 MX MX2021005804A patent/MX2021005804A/es unknown
- 2019-11-14 AU AU2019384498A patent/AU2019384498A1/en active Pending
- 2019-11-14 JP JP2021518693A patent/JP2022509906A/ja active Pending
- 2019-11-14 KR KR1020217012320A patent/KR20210089150A/ko active Search and Examination
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2020
- 2020-08-30 US US17/006,858 patent/US11157306B2/en active Active
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2021
- 2021-04-08 ZA ZA2021/02321A patent/ZA202102321B/en unknown
- 2021-05-21 PH PH12021551164A patent/PH12021551164A1/en unknown
Also Published As
Publication number | Publication date |
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EP4418129A2 (en) | 2024-08-21 |
US20200159558A1 (en) | 2020-05-21 |
US20200394065A1 (en) | 2020-12-17 |
BR112021008419A2 (pt) | 2021-09-14 |
IL283228A (en) | 2021-07-29 |
US10761876B2 (en) | 2020-09-01 |
EP4418129A3 (en) | 2024-10-02 |
KR20210089150A (ko) | 2021-07-15 |
IL283228B2 (en) | 2024-04-01 |
JP2022509906A (ja) | 2022-01-25 |
IL283228B1 (en) | 2023-12-01 |
CN113168379A (zh) | 2021-07-23 |
ZA202102321B (en) | 2022-06-29 |
WO2020106533A1 (en) | 2020-05-28 |
AU2019384498A1 (en) | 2021-05-13 |
EP3884392B1 (en) | 2024-07-17 |
EP3884392A1 (en) | 2021-09-29 |
US11157306B2 (en) | 2021-10-26 |
PH12021551164A1 (en) | 2021-10-25 |
CA3116380A1 (en) | 2020-05-28 |
SG11202104744UA (en) | 2021-06-29 |
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