MX2017016200A - Arquitectura basada en bloques con ejecucion paralela de bloques sucesivos. - Google Patents
Arquitectura basada en bloques con ejecucion paralela de bloques sucesivos.Info
- Publication number
- MX2017016200A MX2017016200A MX2017016200A MX2017016200A MX2017016200A MX 2017016200 A MX2017016200 A MX 2017016200A MX 2017016200 A MX2017016200 A MX 2017016200A MX 2017016200 A MX2017016200 A MX 2017016200A MX 2017016200 A MX2017016200 A MX 2017016200A
- Authority
- MX
- Mexico
- Prior art keywords
- block
- based architecture
- parallel execution
- successive blocks
- instructions
- Prior art date
Links
- 238000000034 method Methods 0.000 abstract 3
- 230000000977 initiatory effect Effects 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
- G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
Abstract
Se describen sistemas, métodos y un almacenamiento legible por computadora para proporcionar el acceso temprano a las direcciones objetivo en las arquitecturas de procesador basadas en bloques. En un ejemplo de la tecnología que se da a conocer, un método para realizar una bifurcación en una arquitectura basada en bloques puede incluir la ejecución de una o más instrucciones de un primer bloque de instrucciones utilizando un primer núcleo de la arquitectura basada en bloques. El método puede incluir, antes de que se haya comprometido el primer bloque de instrucciones, iniciar la ejecución no especulativa de las instrucciones de un segundo bloque de instrucciones.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/752,636 US20160378488A1 (en) | 2015-06-26 | 2015-06-26 | Access to target address |
PCT/US2016/038854 WO2016210031A1 (en) | 2015-06-26 | 2016-06-23 | Block-based architecture with parallel execution of successive blocks |
Publications (1)
Publication Number | Publication Date |
---|---|
MX2017016200A true MX2017016200A (es) | 2018-03-01 |
Family
ID=56369217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2017016200A MX2017016200A (es) | 2015-06-26 | 2016-06-23 | Arquitectura basada en bloques con ejecucion paralela de bloques sucesivos. |
Country Status (15)
Country | Link |
---|---|
US (1) | US20160378488A1 (es) |
EP (2) | EP3314401B1 (es) |
JP (1) | JP2018519602A (es) |
KR (1) | KR20180021812A (es) |
CN (1) | CN107810478A (es) |
AU (1) | AU2016281603A1 (es) |
BR (1) | BR112017024351A2 (es) |
CA (1) | CA2986061A1 (es) |
CL (1) | CL2017003263A1 (es) |
CO (1) | CO2017013272A2 (es) |
HK (1) | HK1246442A1 (es) |
IL (1) | IL256171A (es) |
MX (1) | MX2017016200A (es) |
PH (1) | PH12017550128A1 (es) |
WO (1) | WO2016210031A1 (es) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10409599B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Decoding information about a group of instructions including a size of the group of instructions |
US10169044B2 (en) | 2015-06-26 | 2019-01-01 | Microsoft Technology Licensing, Llc | Processing an encoding format field to interpret header information regarding a group of instructions |
US10191747B2 (en) | 2015-06-26 | 2019-01-29 | Microsoft Technology Licensing, Llc | Locking operand values for groups of instructions executed atomically |
US9952867B2 (en) | 2015-06-26 | 2018-04-24 | Microsoft Technology Licensing, Llc | Mapping instruction blocks based on block size |
US10409606B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Verifying branch targets |
US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
US9946548B2 (en) | 2015-06-26 | 2018-04-17 | Microsoft Technology Licensing, Llc | Age-based management of instruction blocks in a processor instruction window |
US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
US10175988B2 (en) | 2015-06-26 | 2019-01-08 | Microsoft Technology Licensing, Llc | Explicit instruction scheduler state information for a processor |
US9940136B2 (en) | 2015-06-26 | 2018-04-10 | Microsoft Technology Licensing, Llc | Reuse of decoded instructions |
US10095519B2 (en) | 2015-09-19 | 2018-10-09 | Microsoft Technology Licensing, Llc | Instruction block address register |
US11531552B2 (en) * | 2017-02-06 | 2022-12-20 | Microsoft Technology Licensing, Llc | Executing multiple programs simultaneously on a processor core |
CN109101276B (zh) | 2018-08-14 | 2020-05-05 | 阿里巴巴集团控股有限公司 | 在cpu中执行指令的方法 |
US10824429B2 (en) * | 2018-09-19 | 2020-11-03 | Microsoft Technology Licensing, Llc | Commit logic and precise exceptions in explicit dataflow graph execution architectures |
CN109783143B (zh) * | 2019-01-25 | 2021-03-09 | 贵州华芯通半导体技术有限公司 | 用于流水线指令流的控制方法和控制设备 |
US20210096861A1 (en) * | 2019-10-01 | 2021-04-01 | Higon Austin R&D Center | System and method to prefetch pointer based structures |
CN111506520B (zh) * | 2020-07-01 | 2020-09-22 | 腾讯科技(深圳)有限公司 | 一种地址生成的方法、相关装置以及存储介质 |
CN117707619A (zh) * | 2023-11-02 | 2024-03-15 | 上海攸化技术管理咨询有限公司 | 指令的编码方式、运算单元、运算模块及运算方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0583089B1 (en) * | 1992-08-12 | 2000-01-26 | Advanced Micro Devices, Inc. | Instruction decoder |
US5832297A (en) * | 1995-04-12 | 1998-11-03 | Advanced Micro Devices, Inc. | Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations |
GB2393274B (en) * | 2002-09-20 | 2006-03-15 | Advanced Risc Mach Ltd | Data processing system having an external instruction set and an internal instruction set |
US7882339B2 (en) * | 2005-06-23 | 2011-02-01 | Intel Corporation | Primitives to enhance thread-level speculation |
JP4339371B2 (ja) * | 2007-03-22 | 2009-10-07 | 株式会社ソニー・コンピュータエンタテインメント | 情報処理装置および情報処理方法 |
SG11201402727WA (en) * | 2011-12-01 | 2014-06-27 | Univ Singapore | Polymorphic heterogeneous multi-core architecture |
US9182986B2 (en) * | 2012-12-29 | 2015-11-10 | Intel Corporation | Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region |
US9594700B2 (en) * | 2013-04-17 | 2017-03-14 | Nvidia Corporation | Speculative memory controller |
-
2015
- 2015-06-26 US US14/752,636 patent/US20160378488A1/en not_active Abandoned
-
2016
- 2016-06-23 WO PCT/US2016/038854 patent/WO2016210031A1/en active Application Filing
- 2016-06-23 MX MX2017016200A patent/MX2017016200A/es unknown
- 2016-06-23 CN CN201680037706.2A patent/CN107810478A/zh not_active Withdrawn
- 2016-06-23 AU AU2016281603A patent/AU2016281603A1/en not_active Abandoned
- 2016-06-23 KR KR1020187001900A patent/KR20180021812A/ko unknown
- 2016-06-23 BR BR112017024351A patent/BR112017024351A2/pt not_active Application Discontinuation
- 2016-06-23 EP EP16736333.2A patent/EP3314401B1/en active Active
- 2016-06-23 JP JP2017566304A patent/JP2018519602A/ja active Pending
- 2016-06-23 EP EP19218262.4A patent/EP3660668A1/en not_active Withdrawn
- 2016-06-23 CA CA2986061A patent/CA2986061A1/en not_active Abandoned
-
2017
- 2017-11-08 PH PH12017550128A patent/PH12017550128A1/en unknown
- 2017-12-07 IL IL256171A patent/IL256171A/en unknown
- 2017-12-19 CL CL2017003263A patent/CL2017003263A1/es unknown
- 2017-12-21 CO CONC2017/0013272A patent/CO2017013272A2/es unknown
-
2018
- 2018-05-07 HK HK18105888.4A patent/HK1246442A1/zh unknown
Also Published As
Publication number | Publication date |
---|---|
EP3314401A1 (en) | 2018-05-02 |
CA2986061A1 (en) | 2016-12-29 |
CN107810478A (zh) | 2018-03-16 |
CO2017013272A2 (es) | 2018-03-20 |
EP3660668A1 (en) | 2020-06-03 |
BR112017024351A2 (pt) | 2018-07-31 |
CL2017003263A1 (es) | 2018-06-29 |
WO2016210031A1 (en) | 2016-12-29 |
KR20180021812A (ko) | 2018-03-05 |
HK1246442A1 (zh) | 2018-09-07 |
AU2016281603A1 (en) | 2017-11-30 |
EP3314401B1 (en) | 2020-02-12 |
US20160378488A1 (en) | 2016-12-29 |
JP2018519602A (ja) | 2018-07-19 |
PH12017550128A1 (en) | 2018-02-26 |
IL256171A (en) | 2018-02-28 |
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