MX2009008092A - Aparatos y metodos para reducir las expulsiones en una jerarquia de cache de nivel multiple. - Google Patents

Aparatos y metodos para reducir las expulsiones en una jerarquia de cache de nivel multiple.

Info

Publication number
MX2009008092A
MX2009008092A MX2009008092A MX2009008092A MX2009008092A MX 2009008092 A MX2009008092 A MX 2009008092A MX 2009008092 A MX2009008092 A MX 2009008092A MX 2009008092 A MX2009008092 A MX 2009008092A MX 2009008092 A MX2009008092 A MX 2009008092A
Authority
MX
Mexico
Prior art keywords
level cache
displaced
methods
cache
higher level
Prior art date
Application number
MX2009008092A
Other languages
English (en)
Inventor
Thomas Philip Speier
James Norris Dieffenderfer
Thomas Andrew Startorius
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009008092A publication Critical patent/MX2009008092A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Las técnicas y métodos se usan para reducir asignaciones a una caché de nivel superior de líneas de caché desplazadas de una caché de nivel inferior. Cuando se determina que las líneas desplazadas ya se han asignado en un nivel superior, las asignaciones de las líneas de la caché desplazadas se evitan en el siguiente nivel de la caché, por lo tanto, reduciendo expulsiones. Para tales fines, una línea se selecciona para desplazarse en una caché de nivel inferior. La información asociada con la línea seleccionada se identifica lo cual indica que la línea seleccionada está presente en una caché de nivel superior. Una asignación de la línea seleccionada en la caché de nivel superior se evita con base en la información identificada. Al evitar una asignación de la línea seleccionada se ahorra energía asociada con la asignación.
MX2009008092A 2008-01-30 2008-01-30 Aparatos y metodos para reducir las expulsiones en una jerarquia de cache de nivel multiple. MX2009008092A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/US2008/052507 WO2008095025A1 (en) 2007-01-31 2008-01-30 Apparatus and methods to reduce castouts in a multi-level cache hierarchy
US11/669,245 US8078803B2 (en) 2008-01-30 2008-01-30 Apparatus and methods to reduce castouts in a multi-level cache hierarchy

Publications (1)

Publication Number Publication Date
MX2009008092A true MX2009008092A (es) 2009-08-12

Family

ID=39512778

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009008092A MX2009008092A (es) 2008-01-30 2008-01-30 Aparatos y metodos para reducir las expulsiones en una jerarquia de cache de nivel multiple.

Country Status (10)

Country Link
US (2) US8078803B2 (es)
EP (2) EP2118754B1 (es)
JP (4) JP2010518487A (es)
KR (1) KR101165132B1 (es)
CN (2) CN101595462B (es)
BR (1) BRPI0806865A2 (es)
CA (1) CA2675046C (es)
MX (1) MX2009008092A (es)
RU (1) RU2438165C2 (es)
WO (1) WO2008095025A1 (es)

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JP2010518487A (ja) 2008-01-30 2010-05-27 クゥアルコム・インコーポレイテッド マルチレベルのキャッシュ階層におけるキャストアウトを低減するための装置および方法
JP2010113593A (ja) 2008-11-07 2010-05-20 Sony Corp 情報処理装置、情報処理方法及び情報処理プログラム
WO2010052799A1 (ja) * 2008-11-10 2010-05-14 富士通株式会社 情報処理装置及びメモリ制御装置
US20110202727A1 (en) * 2010-02-18 2011-08-18 Qualcomm Incorporated Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache
US9201794B2 (en) * 2011-05-20 2015-12-01 International Business Machines Corporation Dynamic hierarchical memory cache awareness within a storage system
US9021206B2 (en) 2011-08-25 2015-04-28 International Business Machines Corporation Use of cache statistics to ration cache hierarchy access
KR101862785B1 (ko) * 2011-10-17 2018-07-06 삼성전자주식회사 타일 기반 렌더링을 위한 캐쉬 메모리 시스템 및 캐슁 방법
WO2014111984A1 (ja) 2013-01-17 2014-07-24 株式会社ソニー・コンピュータエンタテインメント 情報処理装置およびファイル管理方法
KR20150132099A (ko) * 2013-03-20 2015-11-25 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 서로 다른 계층 레벨의 메모리 노드를 가진 메모리 시스템에서의 데이터 캐싱
US9854052B2 (en) * 2013-09-27 2017-12-26 Sap Se Business object attachments and expiring URLs
JP2015088146A (ja) * 2013-11-01 2015-05-07 株式会社ソニー・コンピュータエンタテインメント 情報処理装置
JP2015176245A (ja) 2014-03-13 2015-10-05 株式会社東芝 情報処理装置及びデータ構造
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CN104932989B (zh) * 2014-03-21 2020-05-19 三星电子株式会社 数据到高速缓冲层次低延迟层级中的机会性高速缓冲注入
JP2016057763A (ja) 2014-09-08 2016-04-21 株式会社東芝 キャッシュ装置、及びプロセッサ
US9684602B2 (en) 2015-03-11 2017-06-20 Kabushiki Kaisha Toshiba Memory access control device, cache memory and semiconductor device
KR101697515B1 (ko) * 2015-12-15 2017-01-18 전남대학교산학협력단 캐시 라인의 태그 거리 상관관계를 이용한 캐시 교체 방법 및 임베디드 시스템
CN109074320B (zh) * 2017-03-08 2023-11-17 华为技术有限公司 一种缓存替换方法,装置和系统
JP7139719B2 (ja) * 2018-06-26 2022-09-21 富士通株式会社 情報処理装置、演算処理装置及び情報処理装置の制御方法
US11782919B2 (en) * 2021-08-19 2023-10-10 International Business Machines Corporation Using metadata presence information to determine when to access a higher-level metadata table

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US20110202727A1 (en) 2010-02-18 2011-08-18 Qualcomm Incorporated Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache

Also Published As

Publication number Publication date
BRPI0806865A2 (pt) 2014-04-29
EP2527987A1 (en) 2012-11-28
JP2010518487A (ja) 2010-05-27
WO2008095025A1 (en) 2008-08-07
RU2009132554A (ru) 2011-03-10
JP2017033584A (ja) 2017-02-09
KR101165132B1 (ko) 2012-07-12
US20120059995A1 (en) 2012-03-08
CN101595462A (zh) 2009-12-02
CA2675046A1 (en) 2008-08-07
US8386716B2 (en) 2013-02-26
EP2118754A1 (en) 2009-11-18
CN102693187A (zh) 2012-09-26
US20080183967A1 (en) 2008-07-31
JP2013069322A (ja) 2013-04-18
CN102693187B (zh) 2016-03-30
CA2675046C (en) 2013-07-30
JP2015111435A (ja) 2015-06-18
CN101595462B (zh) 2012-04-25
US8078803B2 (en) 2011-12-13
EP2118754B1 (en) 2013-07-03
KR20090115799A (ko) 2009-11-06
JP6392286B2 (ja) 2018-09-19
RU2438165C2 (ru) 2011-12-27
JP6009589B2 (ja) 2016-10-19

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