MX2007013394A - Archivos de registro para un procesador de senales digitales que opera en un ambiente multihilo distribuido. - Google Patents

Archivos de registro para un procesador de senales digitales que opera en un ambiente multihilo distribuido.

Info

Publication number
MX2007013394A
MX2007013394A MX2007013394A MX2007013394A MX2007013394A MX 2007013394 A MX2007013394 A MX 2007013394A MX 2007013394 A MX2007013394 A MX 2007013394A MX 2007013394 A MX2007013394 A MX 2007013394A MX 2007013394 A MX2007013394 A MX 2007013394A
Authority
MX
Mexico
Prior art keywords
register files
digital signal
signal processor
processor operating
threaded environment
Prior art date
Application number
MX2007013394A
Other languages
English (en)
Inventor
Erich Plondke
Lucian Codrescu
Muhammad Ahmed
William C Anderson
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2007013394A publication Critical patent/MX2007013394A/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Se describe un dispositivo procesador que incluye una memoria y un secuenciador que es sensible a la memoria. El secuenciador soporta instrucciones de tipo palabra de instrucciones muy larga (VLIW) y al menos un paquete de instrucciones VLIW utiliza un numero determinado de operadores durante la ejecucion. El dispositivo procesador incluye ademas una pluralidad de unidades de ejecucion de instrucciones sensible al secuenciador y una pluralidad de archivos de registro. Cada pluralidad de archivos de registro incluye una pluralidad de registros y la pluralidad de archivos de registros se acopla a la pluralidad de unidades de ejecucion de instrucciones. Ademas, cada pluralidad de archivos de registro incluye un numero determinado de puertos de lectura de daos y el numero de puertos de lectura de datos de cada pluralidad de archivos de registro es menor que el numero de operadores utilizados por al menos un paquete de instrucciones VLIW.
MX2007013394A 2005-04-26 2006-04-24 Archivos de registro para un procesador de senales digitales que opera en un ambiente multihilo distribuido. MX2007013394A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/115,916 US8713286B2 (en) 2005-04-26 2005-04-26 Register files for a digital signal processor operating in an interleaved multi-threaded environment
PCT/US2006/015391 WO2006116258A2 (en) 2005-04-26 2006-04-24 Register files for a digital signal processor operating in an interleaved multi-threaded environment

Publications (1)

Publication Number Publication Date
MX2007013394A true MX2007013394A (es) 2008-01-21

Family

ID=36649497

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2007013394A MX2007013394A (es) 2005-04-26 2006-04-24 Archivos de registro para un procesador de senales digitales que opera en un ambiente multihilo distribuido.

Country Status (5)

Country Link
US (2) US8713286B2 (es)
CN (2) CN105700852B (es)
MX (1) MX2007013394A (es)
TW (1) TW200710718A (es)
WO (1) WO2006116258A2 (es)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8713286B2 (en) 2005-04-26 2014-04-29 Qualcomm Incorporated Register files for a digital signal processor operating in an interleaved multi-threaded environment
WO2007143278A2 (en) 2006-04-12 2007-12-13 Soft Machines, Inc. Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
EP2122461A4 (en) 2006-11-14 2010-03-24 Soft Machines Inc DEVICE AND METHOD FOR PROCESSING COMMUNICATIONS IN A MULTITHREAD ARCHITECTURE WITH CONTEXT CHANGES
US7739481B1 (en) * 2007-09-06 2010-06-15 Altera Corporation Parallelism with variable partitioning and threading
US8516228B2 (en) * 2008-03-19 2013-08-20 International Business Machines Corporation Supporting partial recycle in a pipelined microprocessor
EP2616928B1 (en) 2010-09-17 2016-11-02 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
US9274793B2 (en) 2011-03-25 2016-03-01 Soft Machines, Inc. Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2012135041A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
EP2689327B1 (en) 2011-03-25 2021-07-28 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
TWI548994B (zh) 2011-05-20 2016-09-11 軟體機器公司 以複數個引擎支援指令序列的執行之互連結構
KR101639853B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 자원들 및 상호접속 구조들의 비집중 할당
EP2783281B1 (en) 2011-11-22 2020-05-13 Intel Corporation A microprocessor accelerated code optimizer
KR101842550B1 (ko) 2011-11-22 2018-03-28 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US9626191B2 (en) * 2011-12-22 2017-04-18 Nvidia Corporation Shaped register file reads
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
CN105247484B (zh) 2013-03-15 2021-02-23 英特尔公司 利用本地分布式标志体系架构来仿真访客集中式标志体系架构的方法
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
EP2972845B1 (en) 2013-03-15 2021-07-07 Intel Corporation A method for executing multithreaded instructions grouped onto blocks
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
TWI681300B (zh) 2014-11-14 2020-01-01 美商凱為有限責任公司 在64位元資料路徑上實行128位元simd操作之方法、系統及電腦可讀取媒體
US9952865B2 (en) * 2015-04-04 2018-04-24 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
CN108628639B (zh) * 2017-03-21 2021-02-12 华为技术有限公司 处理器和指令调度方法
US11126588B1 (en) * 2020-07-28 2021-09-21 Shenzhen GOODIX Technology Co., Ltd. RISC processor having specialized registers
US20220121487A1 (en) * 2020-10-20 2022-04-21 Micron Technology, Inc. Thread scheduling control and memory splitting in a barrel processor

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US539989A (en) * 1895-05-28 John a
DE69325785T2 (de) 1992-12-29 2000-02-17 Koninkl Philips Electronics Nv Verbesserte Architektur für Prozessor mit sehr langem Befehlswort
US6002880A (en) 1992-12-29 1999-12-14 Philips Electronics North America Corporation VLIW processor with less instruction issue slots than functional units
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
US5644780A (en) 1995-06-02 1997-07-01 International Business Machines Corporation Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors
US5764943A (en) * 1995-12-28 1998-06-09 Intel Corporation Data path circuitry for processor having multiple instruction pipelines
EP0881575A4 (en) * 1996-02-16 2002-04-17 Hitachi Ltd MULTIPLE ACCESS MEMORY AND DATA PROCESSOR PROVIDING ACCESS TO THE MEMORY
JP2806359B2 (ja) * 1996-04-30 1998-09-30 日本電気株式会社 命令処理方法及び命令処理装置
US5924117A (en) * 1996-12-16 1999-07-13 International Business Machines Corporation Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto
US6055628A (en) * 1997-01-24 2000-04-25 Texas Instruments Incorporated Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
US6314511B2 (en) * 1997-04-03 2001-11-06 University Of Washington Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers
US6014739A (en) 1997-10-27 2000-01-11 Advanced Micro Devices, Inc. Increasing general registers in X86 processors
US6161166A (en) * 1997-11-10 2000-12-12 International Business Machines Corporation Instruction cache for multithreaded processor
US6076154A (en) * 1998-01-16 2000-06-13 U.S. Philips Corporation VLIW processor has different functional units operating on commands of different widths
US6192461B1 (en) * 1998-01-30 2001-02-20 International Business Machines Corporation Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle
US6092175A (en) * 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6718457B2 (en) * 1998-12-03 2004-04-06 Sun Microsystems, Inc. Multiple-thread processor for threaded software applications
US6523055B1 (en) * 1999-01-20 2003-02-18 Lsi Logic Corporation Circuit and method for multiplying and accumulating the sum of two products in a single cycle
US6397324B1 (en) 1999-06-18 2002-05-28 Bops, Inc. Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file
US6654870B1 (en) 1999-06-21 2003-11-25 Pts Corporation Methods and apparatus for establishing port priority functions in a VLIW processor
US6457173B1 (en) 1999-08-20 2002-09-24 Hewlett-Packard Company Automatic design of VLIW instruction formats
US6385757B1 (en) 1999-08-20 2002-05-07 Hewlett-Packard Company Auto design of VLIW processors
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
US6320813B1 (en) 2000-03-02 2001-11-20 Sun Microsystems, Inc. Decoding of a register file
TW539989B (en) 2000-03-31 2003-07-01 Intel Corp Multiplier architecture in a general purpose processor optimized for efficient multi-input addition
JP2004512716A (ja) * 2000-10-02 2004-04-22 アルテラ・コーポレイション 専用プロセッサ装置を含むプログラマブルロジック集積回路装置
US7127588B2 (en) * 2000-12-05 2006-10-24 Mindspeed Technologies, Inc. Apparatus and method for an improved performance VLIW processor
EP1564749B8 (en) * 2000-12-20 2009-02-18 Fujitsu Microelectronics Limited Multi-port memory based on DRAM core
US7028286B2 (en) * 2001-04-13 2006-04-11 Pts Corporation Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture
US7179275B2 (en) * 2001-06-18 2007-02-20 Rex Medical, L.P. Vein filter
US6954846B2 (en) 2001-08-07 2005-10-11 Sun Microsystems, Inc. Microprocessor and method for giving each thread exclusive access to one register file in a multi-threading mode and for giving an active thread access to multiple register files in a single thread mode
US7206559B2 (en) * 2001-10-16 2007-04-17 Hewlett-Packard Development Company, L.P. System and method for a mobile computing device to control appliances
WO2003036468A1 (en) * 2001-10-24 2003-05-01 Telefonaktiebolaget Lm Ericsson (Publ) An arrangement and a method in processor technology
US7100022B1 (en) * 2002-02-28 2006-08-29 Mindspeed Technologies, Inc. Area and power efficient VLIW processor with improved speed
US6724416B1 (en) 2002-10-01 2004-04-20 Jianxin Liu Image transceiving telephone with integrated digital camera
US6904511B2 (en) * 2002-10-11 2005-06-07 Sandbridge Technologies, Inc. Method and apparatus for register file port reduction in a multithreaded processor
US7657893B2 (en) 2003-04-23 2010-02-02 International Business Machines Corporation Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor
US20040266480A1 (en) * 2003-06-27 2004-12-30 Hjelt Kari Tapani System and method for implementing sensor functionality in mobile devices
US7940932B2 (en) * 2004-04-08 2011-05-10 Texas Instruments Incorporated Methods, apparatus, and systems for securing SIM (subscriber identity module) personalization and other data on a first processor and secure communication of the SIM data to a second processor
US7398347B1 (en) * 2004-07-14 2008-07-08 Altera Corporation Methods and apparatus for dynamic instruction controlled reconfigurable register file
ATE456829T1 (de) * 2004-09-22 2010-02-15 Koninkl Philips Electronics Nv Datenverarbeitungsschaltung mit funktionseinheiten mit gemeinsamen leseports
US7590824B2 (en) * 2005-03-29 2009-09-15 Qualcomm Incorporated Mixed superscalar and VLIW instruction issuing and processing method and system
US8713286B2 (en) 2005-04-26 2014-04-29 Qualcomm Incorporated Register files for a digital signal processor operating in an interleaved multi-threaded environment

Also Published As

Publication number Publication date
WO2006116258A2 (en) 2006-11-02
TW200710718A (en) 2007-03-16
US20140181468A1 (en) 2014-06-26
US8713286B2 (en) 2014-04-29
CN105700852A (zh) 2016-06-22
US9235418B2 (en) 2016-01-12
WO2006116258A3 (en) 2007-10-04
CN105700852B (zh) 2019-04-16
CN101203830B (zh) 2016-02-10
US20060242384A1 (en) 2006-10-26
CN101203830A (zh) 2008-06-18

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