MX173004B - Sistema de control de microprocesadora doble - Google Patents

Sistema de control de microprocesadora doble

Info

Publication number
MX173004B
MX173004B MX010951A MX1095188A MX173004B MX 173004 B MX173004 B MX 173004B MX 010951 A MX010951 A MX 010951A MX 1095188 A MX1095188 A MX 1095188A MX 173004 B MX173004 B MX 173004B
Authority
MX
Mexico
Prior art keywords
microprocessor
elements
address
data
control system
Prior art date
Application number
MX010951A
Other languages
English (en)
Inventor
Scott W Smith
Thomas O Holtey
Thomas L Murray Jr
Wayne A Perzan
Original Assignee
Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Bull filed Critical Honeywell Bull
Publication of MX173004B publication Critical patent/MX173004B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
  • Microcomputers (AREA)

Abstract

La presente invención se refiere a un sistema de control de microprocesadora doble, que comprende: una primera microprocesadora; primeros ductos de direcciones y datos, asociados a dicha primera microprocesadora; una segunda microprocesadora; segundos ductos de direcciones y datos, asociados a dicha segunda microprocesadora; elementos de memoria que tienen ductos de direcciones y datos, asociados a ellos; elementos que interacoplan a los ductos de datos de la primera y de la segunda microprocesadora al ducto de datos de los elementos de memoria; elementos que interacoplan a los ductos de direcciones de la primera y de la segunda microprocesadora al ducto de direcciones de los elementos de memoria, con la inclusión de elementos para establecer números de canales, que corresponden a tableros de línea de dichos elementos de memoria, para ambas microprocesadoras, y elementos de control para cambiar los números de los canales, pero evitando que los elementos para establecimiento para cada microprocesadora, direcciones al mismo canal simultáneamente.
MX010951A 1987-03-31 1988-03-30 Sistema de control de microprocesadora doble MX173004B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/032,902 US4979104A (en) 1987-03-31 1987-03-31 Dual microprocessor control system

Publications (1)

Publication Number Publication Date
MX173004B true MX173004B (es) 1994-01-28

Family

ID=21867476

Family Applications (1)

Application Number Title Priority Date Filing Date
MX010951A MX173004B (es) 1987-03-31 1988-03-30 Sistema de control de microprocesadora doble

Country Status (17)

Country Link
US (1) US4979104A (es)
EP (1) EP0289771B1 (es)
JP (1) JPS6478359A (es)
KR (1) KR930003402B1 (es)
CN (1) CN1020810C (es)
AU (1) AU608582B2 (es)
BR (1) BR8801411A (es)
CA (1) CA1301945C (es)
DE (1) DE3850903T2 (es)
DK (1) DK181788A (es)
FI (1) FI881449A (es)
IL (1) IL85863A (es)
MX (1) MX173004B (es)
NO (1) NO881409L (es)
NZ (1) NZ223881A (es)
PH (1) PH25694A (es)
YU (1) YU64888A (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155857A (en) * 1987-05-29 1992-10-13 Hitachi, Ltd. Communication processing system in which communication by terminals is controlled according to a terminal management table
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features
CN1081367C (zh) * 1995-11-23 2002-03-20 联华电子股份有限公司 限定使用次数的集成电路
US8145869B2 (en) * 2007-01-12 2012-03-27 Broadbus Technologies, Inc. Data access and multi-chip controller

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651482A (en) * 1968-04-03 1972-03-21 Honeywell Inc Interlocking data subprocessors
US3670306A (en) * 1971-03-01 1972-06-13 Honeywell Inf Systems Process for data communication between data processing systems
US4318174A (en) * 1975-12-04 1982-03-02 Tokyo Shibaura Electric Co., Ltd. Multi-processor system employing job-swapping between different priority processors
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
US4425616A (en) * 1979-11-06 1984-01-10 Frederick Electronic Corporation High-speed time share processor
US4488231A (en) * 1980-09-29 1984-12-11 Honeywell Information Systems Inc. Communication multiplexer having dual microprocessors
US4482982A (en) * 1980-09-29 1984-11-13 Honeywell Information Systems Inc. Communication multiplexer sharing a free running timer among multiple communication lines
JPS59202561A (ja) * 1983-05-04 1984-11-16 Nec Corp マルチマイクロプロセツサシステムにおけるメモリアクセス方式
DE3335357A1 (de) * 1983-09-29 1985-04-11 Siemens AG, 1000 Berlin und 8000 München Systemarchitektur fuer ein signalprozessorsystem zur funktionalen integration einer automatischen spracheingabe/-ausgabe
JPS60247763A (ja) * 1984-05-24 1985-12-07 Matsushita Electric Ind Co Ltd ブロツク単位並行処理メモリ

Also Published As

Publication number Publication date
KR930003402B1 (ko) 1993-04-26
CN1020810C (zh) 1993-05-19
EP0289771A3 (en) 1990-07-11
DE3850903D1 (de) 1994-09-08
NO881409D0 (no) 1988-03-29
FI881449A (fi) 1988-10-01
KR880011653A (ko) 1988-10-29
CN88102351A (zh) 1988-11-02
PH25694A (en) 1991-09-04
AU608582B2 (en) 1991-04-11
IL85863A0 (en) 1988-09-30
DE3850903T2 (de) 1995-04-06
EP0289771B1 (en) 1994-08-03
EP0289771A2 (en) 1988-11-09
AU1380188A (en) 1988-09-29
JPH0583938B2 (es) 1993-11-30
CA1301945C (en) 1992-05-26
IL85863A (en) 1991-07-18
YU64888A (en) 1991-01-28
US4979104A (en) 1990-12-18
NZ223881A (en) 1990-02-26
JPS6478359A (en) 1989-03-23
BR8801411A (pt) 1988-11-01
NO881409L (no) 1988-10-03
DK181788A (da) 1989-02-07
FI881449A0 (fi) 1988-03-28
DK181788D0 (da) 1988-03-30

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