LU64263A1 - - Google Patents

Info

Publication number
LU64263A1
LU64263A1 LU64263DA LU64263A1 LU 64263 A1 LU64263 A1 LU 64263A1 LU 64263D A LU64263D A LU 64263DA LU 64263 A1 LU64263 A1 LU 64263A1
Authority
LU
Luxembourg
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19702056535 external-priority patent/DE2056535C/de
Application filed filed Critical
Publication of LU64263A1 publication Critical patent/LU64263A1/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
LU64263D 1970-11-17 1971-11-15 LU64263A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702056535 DE2056535C (de) 1970-11-17 Schaltungsanordnung für Fernmelde-, insbesondere Fernsprechvermittlungsanlagen, die durch mindestens zwei Rechner zentral gesteuert werden

Publications (1)

Publication Number Publication Date
LU64263A1 true LU64263A1 (de) 1972-06-02

Family

ID=5788371

Family Applications (1)

Application Number Title Priority Date Filing Date
LU64263D LU64263A1 (de) 1970-11-17 1971-11-15

Country Status (8)

Country Link
AT (1) AT316662B (de)
BE (1) BE775460A (de)
CH (1) CH535522A (de)
FR (1) FR2114590A5 (de)
GB (1) GB1338943A (de)
IT (1) IT941161B (de)
LU (1) LU64263A1 (de)
NL (1) NL158351B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system

Also Published As

Publication number Publication date
DE2056535B2 (de) 1972-05-04
FR2114590A5 (de) 1972-06-30
DE2056535A1 (de) 1972-05-04
IT941161B (it) 1973-03-01
GB1338943A (en) 1973-11-28
AT316662B (de) 1974-07-25
CH535522A (de) 1973-03-31
NL7115845A (de) 1972-05-19
BE775460A (fr) 1972-05-17
NL158351B (nl) 1978-10-16

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