FR2114590A5 - - Google Patents

Info

Publication number
FR2114590A5
FR2114590A5 FR7140497A FR7140497A FR2114590A5 FR 2114590 A5 FR2114590 A5 FR 2114590A5 FR 7140497 A FR7140497 A FR 7140497A FR 7140497 A FR7140497 A FR 7140497A FR 2114590 A5 FR2114590 A5 FR 2114590A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7140497A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19702056535 external-priority patent/DE2056535C/de
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of FR2114590A5 publication Critical patent/FR2114590A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
FR7140497A 1970-11-17 1971-11-12 Expired FR2114590A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702056535 DE2056535C (de) 1970-11-17 Schaltungsanordnung für Fernmelde-, insbesondere Fernsprechvermittlungsanlagen, die durch mindestens zwei Rechner zentral gesteuert werden

Publications (1)

Publication Number Publication Date
FR2114590A5 true FR2114590A5 (de) 1972-06-30

Family

ID=5788371

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7140497A Expired FR2114590A5 (de) 1970-11-17 1971-11-12

Country Status (8)

Country Link
AT (1) AT316662B (de)
BE (1) BE775460A (de)
CH (1) CH535522A (de)
FR (1) FR2114590A5 (de)
GB (1) GB1338943A (de)
IT (1) IT941161B (de)
LU (1) LU64263A1 (de)
NL (1) NL158351B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system

Also Published As

Publication number Publication date
DE2056535A1 (de) 1972-05-04
BE775460A (fr) 1972-05-17
NL7115845A (de) 1972-05-19
NL158351B (nl) 1978-10-16
AT316662B (de) 1974-07-25
GB1338943A (en) 1973-11-28
CH535522A (de) 1973-03-31
LU64263A1 (de) 1972-06-02
IT941161B (it) 1973-03-01
DE2056535B2 (de) 1972-05-04

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Legal Events

Date Code Title Description
ST Notification of lapse