LU61238A1 - - Google Patents
Info
- Publication number
- LU61238A1 LU61238A1 LU61238DA LU61238A1 LU 61238 A1 LU61238 A1 LU 61238A1 LU 61238D A LU61238D A LU 61238DA LU 61238 A1 LU61238 A1 LU 61238A1
- Authority
- LU
- Luxembourg
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Shift Register Type Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19691933907 DE1933907A1 (de) | 1969-07-03 | 1969-07-03 | Pufferspeicher |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| LU61238A1 true LU61238A1 (xx) | 1971-07-06 |
Family
ID=5738826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| LU61238D LU61238A1 (xx) | 1969-07-03 | 1970-07-01 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3665424A (xx) |
| BE (1) | BE752954A (xx) |
| DE (1) | DE1933907A1 (xx) |
| FR (1) | FR2050467A1 (xx) |
| GB (1) | GB1293032A (xx) |
| LU (1) | LU61238A1 (xx) |
| NL (1) | NL7009202A (xx) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710516B2 (xx) * | 1972-12-13 | 1982-02-26 | ||
| US4163291A (en) * | 1975-10-15 | 1979-07-31 | Tokyo Shibaura Electric Co., Ltd. | Input-output control circuit for FIFO memory |
| US4125877A (en) * | 1976-11-26 | 1978-11-14 | Motorola, Inc. | Dual port random access memory storage cell |
| US4296477A (en) * | 1979-11-19 | 1981-10-20 | Control Data Corporation | Register device for transmission of data having two data ranks one of which receives data only when the other is full |
-
1969
- 1969-07-03 DE DE19691933907 patent/DE1933907A1/de active Pending
-
1970
- 1970-06-23 NL NL7009202A patent/NL7009202A/xx unknown
- 1970-06-29 US US50562A patent/US3665424A/en not_active Expired - Lifetime
- 1970-06-30 FR FR7024182A patent/FR2050467A1/fr not_active Withdrawn
- 1970-07-01 LU LU61238D patent/LU61238A1/xx unknown
- 1970-07-02 GB GB32054/70A patent/GB1293032A/en not_active Expired
- 1970-07-03 BE BE752954D patent/BE752954A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR2050467A1 (xx) | 1971-04-02 |
| BE752954A (fr) | 1971-01-04 |
| NL7009202A (xx) | 1971-01-05 |
| DE1933907A1 (de) | 1971-03-11 |
| GB1293032A (en) | 1972-10-18 |
| US3665424A (en) | 1972-05-23 |