FR2050467A1 - - Google Patents

Info

Publication number
FR2050467A1
FR2050467A1 FR7024182A FR7024182A FR2050467A1 FR 2050467 A1 FR2050467 A1 FR 2050467A1 FR 7024182 A FR7024182 A FR 7024182A FR 7024182 A FR7024182 A FR 7024182A FR 2050467 A1 FR2050467 A1 FR 2050467A1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7024182A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2050467A1 publication Critical patent/FR2050467A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
FR7024182A 1969-07-03 1970-06-30 Withdrawn FR2050467A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19691933907 DE1933907A1 (de) 1969-07-03 1969-07-03 Pufferspeicher

Publications (1)

Publication Number Publication Date
FR2050467A1 true FR2050467A1 (fr) 1971-04-02

Family

ID=5738826

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7024182A Withdrawn FR2050467A1 (fr) 1969-07-03 1970-06-30

Country Status (7)

Country Link
US (1) US3665424A (fr)
BE (1) BE752954A (fr)
DE (1) DE1933907A1 (fr)
FR (1) FR2050467A1 (fr)
GB (1) GB1293032A (fr)
LU (1) LU61238A1 (fr)
NL (1) NL7009202A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710516B2 (fr) * 1972-12-13 1982-02-26
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
US4296477A (en) * 1979-11-19 1981-10-20 Control Data Corporation Register device for transmission of data having two data ranks one of which receives data only when the other is full

Also Published As

Publication number Publication date
GB1293032A (en) 1972-10-18
DE1933907A1 (de) 1971-03-11
US3665424A (en) 1972-05-23
BE752954A (fr) 1971-01-04
LU61238A1 (fr) 1971-07-06
NL7009202A (fr) 1971-01-05

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Legal Events

Date Code Title Description
ST Notification of lapse