LU500903B1 - Low Noise Amplifier Bypass Structure - Google Patents
Low Noise Amplifier Bypass Structure Download PDFInfo
- Publication number
- LU500903B1 LU500903B1 LU500903A LU500903A LU500903B1 LU 500903 B1 LU500903 B1 LU 500903B1 LU 500903 A LU500903 A LU 500903A LU 500903 A LU500903 A LU 500903A LU 500903 B1 LU500903 B1 LU 500903B1
- Authority
- LU
- Luxembourg
- Prior art keywords
- transistor
- low noise
- noise amplifier
- blocking capacitor
- drain
- Prior art date
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- 239000003990 capacitor Substances 0.000 claims abstract description 38
- 230000000903 blocking effect Effects 0.000 claims abstract description 32
- 230000003321 amplification Effects 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 240000008042 Zea mays Species 0.000 claims 1
- 235000005824 Zea mays ssp. parviglumis Nutrition 0.000 claims 1
- 235000002017 Zea mays subsp mays Nutrition 0.000 claims 1
- 235000005822 corn Nutrition 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000010295 mobile communication Methods 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7239—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
A low noise amplifier bypass structure, which is characterized the RF input is connected to the drain of a first transistor through the DC blocking capacitor, the source of the first transistor is connected to the second transistor drain, and the source of the second transistor is connected to the RF output through the DC blocking capacitor C2; the first transistor gate and the second transistor gate are both connected with bias voltage through gate resistance; the input of the inverter is connected with a bias voltage, the output of the inverter is connected with the third transistor gate through a gate resistance RG, the third transistor source is connected to ground through the DC blocking capacitor C3, the third transistor drain is connected with one end of the DC blocking capacitor C4, and the other end of the DC blocking capacitor is connected to ground through the resistance. Figure 2
Description
DESCRIPTION Low Noise Amplifier Bypass Structure
TECHNICAL FIELD The invention relates to a RF low noise amplifier circuit for wireless communication, in particular to a low noise amplifier bypass structure.
BACKGROUND Nowadays, wireless communication technology 1s constantly developing and expanding, and its function and demand are also increasing. Low noise amplifier (LNA) is a key component of the RF receiver front end, which needs to meet the key specifications of low noise, high linearity, appropriate gain and unconditional stability in cellular mobile communication applications. Wi-Fi technology, as a supplement to cellular mobile communication, can perform multi-access and hand-in, which is very suitable for indoor wireless LAN.
The low noise amplifier for Wi-Fi applications has a wide range of signal strength received by the antenna. When the input signal is too large, it will easily lead to gain compression and serious harmonic distortion of the low noise amplifier, which will deteriorate the receiving sensitivity and even damage the subsequent components of the receiver. The special requirements for signal quality put forward new requirements for this kind of low noise amplifier. When the signal intensity is high, it is allowed to turn off the amplifier, so that the signal can be bypassed from other channels to ensure the normal operation of the RF receiver.
SUMMARY The purpose of the present invention is to provide a low noise amplifier bypass structure, which is used to realize high isolation and high linearity bypass circuit, and to complete dual functions of RF signal amplification and RF signal bypass.
In order to achieve the above tasks, the invention adopts the following technical scheme: a low noise amplifier bypass structure comprises a DC blocking capacitor C1, a DC blocking capacitor Co, a DC blocking capacitor C3, a DC blocking capacitor C4, a resistance Ri, a first transistor Mi, a second transistor M», a third transistor M; and an inverter, wherein: the RF input port RFin is connected to the drain of the first transistor M through the DC blocking capacitor C1, and the source of the first transistor M1 is connected to the drain of the second transistor Maz, which is connected to the RF output port RFout through the DC blocking capacitor Cs; the gate of the first transistor M1 and the gate of the second transistor M are both connected with a bias voltage Vip through the gate resistance Rg; the input of the inverter is connected with the bias voltage Vgp, the output of the inverter is connected with the gate of the third transistor M; through gate resistance Rg, the source of the third transistor Ms is connected to ground through the DC blocking capacitor Cs, the drain of the third transistor M3 is connected with one end of the DC blocking capacitor C4, the source of the first transistor M1 and the drain of the second transistor Ma, and the other end of the DC blocking capacitor C4 is connected to ground through the resistance Ri; and a drain-to-source resistance Rps is arranged between the drain and source of the first transistor My, the drain and source of the second transistor M» and the drain and source of the third transistor Ms.
Typically, the value of Rı is less than 10 ohms.
Furthermore, the low noise amplifier bypass structure is connected in parallel with both ends of the low noise amplifier.
Furthermore, when the bias voltage Var is at high potential, the low noise amplifier is in bypass mode, and the first transistor M1 and the second transistor Mz in the bypass circuit are in the on state, which are equivalent to on-resistance Roni and Rom respectively; the third transistor Ms is in the off state, which is equivalent to an off capacitor Corrs; at this time, the low noise amplifier will be bypassed, and the RF signal will mainly go through the bypass structure from the input port RFin to the output port RFout - Furthermore, when the bias voltage Vp is at low potential, the low noise amplifier is in amplification mode, and the first transistor M; and the second transistor M3 in the bypass circuit are in the off state, which are equivalent to the off capacitors Cor and Cor respectively; the third transistor M3 is in the on state, which is equivalent to an on-
resistance Rons; the RF signal mainly enters the input of the amplifier, and the leakage signal flowing through the bypass circuit will flow to the ground through the parallel branch of the bypass circuit.
Compared with the prior art, the invention has the following technical characteristics:
1. the low noise amplifier bypass circuit structure provided by the invention can improve the sensitivity and reliability of the receiver; when the input of the low noise amplifier is a strong signal power (typically between 0 and 10 dBm in WLAN application), it is used to bypass the signal to save power consumption and prevent damage to subsequent components of the receiver; when the input signal is small, it is used to isolate the signal to complete the amplification function.
2. the low noise amplifier bypass circuit structure provided by the invention can provide high isolation and linearity when the amplifier is in amplification mode, and can provide reasonable loss in bypass mode, thereby improving the linearity of the low noise amplifier.
BRIEF DESCRIPTION OF THE FIGURES Figure 1 A schematic diagram of a low noise amplifier with bypass circuit; Figure 2 A schematic diagram of the low noise amplifier bypass structure of the present invention Figure 3 An equivalent circuit when the low noise amplifier bypass structure of the present invention is in bypass mode; Figure 4 An equivalent circuit when the low noise amplifier bypass structure of the present invention is in amplification mode Figure 5 A simulation curve of noise figure of a 5.15-5.85 GHz low noise amplifier using the bypass structure of the present invention in amplification and bypass modes Figure 6 A gain simulation curve of a 5.15-5.85 GHz low noise amplifier using the bypass structure of the present invention in amplification and bypass modes Figure 7 An IIP3 simulation curve of a 5.15-5.85 GHz low noise amplifier using the bypass structure of the present invention in amplification and bypass modes
DESCRIPTION OF THE INVENTION The embodiment of the invention discloses a low noise amplifier bypass structure, which comprises a DC blocking capacitor C1, a DC blocking capacitor Cz, a DC blocking capacitor Cs, a DC blocking capacitor C4, a resistance Ri, a first transistor M1, a second transistor M3, a third transistor M3 and an inverter, wherein: the RF input port RFin is connected to the drain of the first transistor M through the DC blocking capacitor Ci, and the source of the first transistor Mi is connected to the drain of the second transistor M», which is connected to the RF output port RFout through the DC blocking capacitor Cs; the gate of the first transistor M1 and the gate of the second transistor M are both connected with a bias voltage Vip through the gate resistance Rg; the input of the inverter is connected with the bias voltage Vgp, the output of the inverter is connected with the gate of the third transistor M; through gate resistance Rg, the source of the third transistor Ms is connected to ground through the DC blocking capacitor Cs, the drain of the third transistor M3 is connected with one end of the DC blocking capacitor C4, the source of the first transistor M1 and the drain of the second transistor Ma, and the other end of the DC blocking capacitor C4 is connected to ground through the resistance Ri; and a drain-source resistance Rpg is arranged between the drain and source of the first transistor My, the drain and source of the second transistor M» and the drain and source of the third transistor Ms.
Optionally, the value of R; is less than 10 ohms.
As shown in Figure 3, when the bias voltage Ver is at high potential (logic "1") (for example, +3.3 V), the low noise amplifier is in bypass mode, and the first transistor M1 and the second transistor Ma in the bypass circuit are in the on state, which are equivalent to on-resistance Roni and Ron respectively; the third transistor Ms is in the off state, which is equivalent to an off capacitor Corrs. At this time, the low noise amplifier will be bypassed, and the RF signal will mainly go through the bypass structure from the input port RFin to the output port RF out.
As shown in Figure 4, when the bias voltage Vp 1s at low potential (logic "0") (for example, 0 V), the low noise amplifier is in amplification mode, and the first transistor Mi and the second transistor Mz in the bypass circuit are in the off state, which are equivalent to the off capacitors Cote and Corr respectively; the third transistor Ms is in the on state, which is equivalent to an on-resistance Rons. The RF signal mainly enters the input of the amplifier, and the leakage signal flowing through the bypass circuit will flow to the ground through the parallel branch of the bypass circuit.
Figure 5, Figure 6 and Figure 7 respectively show the simulation curves of noise figure, gain and IIP3 of a 5.15-5.85 GHz low noise amplifier adopting the bypass structure of the present invention in amplification and bypass modes. The results show that the circuit can provide noise figure below 1.3 dB, gain above 13 dB and IIP 3 above 7 dBm in amplification mode; in the bypass mode, the noise figure in the operation frequency is between 6.5 and 7 dB, the loss is between 8 and 9 dB, and the IIP3 is greater than 23 dBm, which can meet the requirements of 5G WLAN mobile communication applications.
It should be noted that, in general, the source and drain of transistors are interchangeable, so in the description of the present invention, the source and drain of all transistors are interchangeable, which is easy for people skilled in the art to understand.
The technical scheme proposed by the invention is not limited to bulk CMOS technology, but can also be extended to the improved process technologies such as SOI CMOS, GaAs pHEMT, GaN HEMT, and SiGe BiCMOS, which is easy to understand for the technicians in the field.
Claims (5)
1. A low noise amplifier bypass structure, which is characterized by comprising a DC blocking capacitor C1, a DC blocking capacitor Cz, a DC blocking capacitor Cs, a DC blocking capacitor Ca, a resistance Rj, a first transistor M1, a second transistor Ma, a third transistor Ms and an inverter, wherein: the RF input RFin is connected to the drain of the first transistor M1 through the DC blocking capacitor C1, and the source of the first transistor M1 is connected to the drain of the second transistor My, which is connected to the RF output RFout through the DC blocking capacitor Cs; the gate of the first transistor M1 and the gate of the second transistor M are both connected with a bias voltage Vip through the gate resistance Rg; the input of the inverter is connected with the bias voltage Vgp, the output of the inverter is connected with the gate of the third transistor M3 through gate resistance Rg, the source of the third transistor Ms is connected to ground through the DC blocking capacitor Cs, the drain of the third transistor M3 is connected with one end of the DC blocking capacitor C4, the source of the first transistor M1 and the drain of the second transistor Ma, and the other end of the DC blocking capacitor C4 is connected to ground through the resistance Ri; and a drain-source resistance Rpg is arranged between the drain and source of the first transistor My, the drain and source of the second transistor M» and the drain and source of the third transistor Ms.
2. The low noise amplifier bypass structure according to claim 1, which is characterized in that the low noise amplifier bypass structure is connected in parallel with both ends of the low noise amplifier.
3. The low noise amplifier bypass structure according to claim 1, which is characterized in that the value of Rı is less than 10 ohms.
4. The low noise amplifier bypass structure according to claim 1, which is characterized in that when the bias voltage Vgp is at high potential, the low noise amplifier is in bypass mode, and the first transistor Mi and the second transistor M3 in the bypass circuit are in on state, which are equivalent to on-resistance Roni and Rom respectively; the third transistor M3 is in an off state, which is equivalent to an off capacitor Corrs; at this time, the low noise amplifier will be bypassed, and the RF signal will mainly go from the input RFin to the output RFout via Ron1 and Rom.
5. The low noise amplifier bypass structure according to claim 1, which is characterized in that when the bias voltage Vgp is at low potential, the low noise amplifier is in amplification mode, and the first transistor M1 and the second transistor Mz in the bypass circuit are in off state, which are equivalent to the off capacitors Corn and Cor respectively; the third transistor M3 is in an on state, which is equivalent to an on- resistance Rons; the RF signal mainly enters the input of the amplifier, and the leakage signal flowing through the bypass circuit will flow to the ground through the parallel branch of the bypass circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| LU500903A LU500903B1 (en) | 2021-11-25 | 2021-11-25 | Low Noise Amplifier Bypass Structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| LU500903A LU500903B1 (en) | 2021-11-25 | 2021-11-25 | Low Noise Amplifier Bypass Structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| LU500903B1 true LU500903B1 (en) | 2022-05-25 |
Family
ID=81827365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| LU500903A LU500903B1 (en) | 2021-11-25 | 2021-11-25 | Low Noise Amplifier Bypass Structure |
Country Status (1)
| Country | Link |
|---|---|
| LU (1) | LU500903B1 (en) |
-
2021
- 2021-11-25 LU LU500903A patent/LU500903B1/en active IP Right Grant
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| Date | Code | Title | Description |
|---|---|---|---|
| FG | Patent granted |
Effective date: 20220525 |