LU101043B1 - Semiconductor shallow trench isolation etching processing device - Google Patents
Semiconductor shallow trench isolation etching processing device Download PDFInfo
- Publication number
- LU101043B1 LU101043B1 LU101043A LU101043A LU101043B1 LU 101043 B1 LU101043 B1 LU 101043B1 LU 101043 A LU101043 A LU 101043A LU 101043 A LU101043 A LU 101043A LU 101043 B1 LU101043 B1 LU 101043B1
- Authority
- LU
- Luxembourg
- Prior art keywords
- gas
- branch
- wafer
- reaction chamber
- reaction
- Prior art date
Links
- 238000005530 etching Methods 0.000 title claims abstract description 17
- 238000002955 isolation Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000007789 gas Substances 0.000 claims abstract description 103
- 239000012495 reaction gas Substances 0.000 claims abstract description 23
- 238000010926 purge Methods 0.000 claims abstract description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 6
- 239000002245 particle Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention discloses a semiconductor shallow trench isolation etching processing device which includes a reaction chamber, a reaction gas pipe and a purger, where a chuck for fixing a wafer is arranged in the reaction chamber; and the reaction gas pipe is configured to convey reaction gas into the reaction chamber. The purger includes a gas pipeline and a gas source, and the gas source is configured to supply a purge gas to the gas pipeline; the gas pipeline is disposed in a chamber wall of the reaction chamber; a gas inlet end of the gas pipeline is connected with the gas source, and gas outlet ends of the gas pipeline are disposed on a chamber side wall of the reaction chamber and configured to convey purse gas towards the upper surface of the wafer and in the direction parallel to the upper surface of the wafer. According to the present invention, particles falling on the upper surface of the wafer can be removed before and after a process is implemented, so that partial etching defects can be overcome, thereby improving product yield.
Description
SEMICONDUCTOR SHALLOW TRENCH ISOLATION ETCHING PROCESSING 4191043
BACKGROUND Technical Field The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor shallow trench isolation etching processing device.
Related Art Shallow trench isolation etching is one of the most important processes in integrated circuit fabrication, which directly affects the electrical properties and stability of a device. For the shallow trench isolation etching process, the control of etching defects is the most critical factor in improving product yield. In actual production, etching defects are mainly caused by large-size particles falling on the surface of a wafer before and after etching, which causes an etched pattern to be destroyed, thereby directly affecting the product yield. Summary Against the aforementioned shortcomings in the prior art, an objective of the present invention is to provide a semiconductor shallow trench isolation etching processing device. In order to achieve the aforementioned objective, the following technical solution is adopted according to the present invention: a semiconductor shallow trench isolation etching processing device, including a reaction chamber and a reaction gas pipe, where a chuck for fixing a wafer is arranged in the reaction chamber; and the reaction gas pipe is configured to convey reaction gas into the reaction chamber; the processing device further includes a purger, and the purger includes a gas pipeline and a gas source, where the gassource is configured to supply a purge gas to the gas pipeline, and the gas pipeline LU101043 is disposed in a chamber wall of the reaction chamber; a gas inlet end of the gas pipeline is connected with the gas source, and gas outlet ends of the gas pipeline are disposed on a chamber side wall of the reaction chamber and configured to convey the purse gas towards the upper surface of the wafer and in the direction parallel to the upper surface of the wafer.
Preferably, the number of the gas outlet ends of the gas pipeline is a plurality, and the gas outlet ends are divided into one or more gas outlet groups; the multiple gas outlet groups are distributed at intervals in the direction perpendicular to the upper surface of the wafer; the plurality of gas outlet ends in the gas outlet groups are distributed at intervals along the chamber side wall of the reaction chamber, and the heights of the gas outlet ends relative to the upper surface of the wafer are the same.
Preferably, the gas pipeline includes a first branch and a second branch; the first branch and the second branch are connected in parallel with each other, and are connected in series between the gas inlet end and the gas outlet ends; the first branch is provided with a first switching valve and a first flow valve, and the first switching valve is configured to open or close the first branch; the first flow valve is configured to adjust a gas flow of the first branch; a second switching valve and a second flow valve are disposed on the second branch, and the second switching valve is configured to open or close the second branch; and the second flow valve is configured to adjust a gas flow of the second branch.
Preferably, the purge gas includes nitrogen or an inert gas.
Due to the adoption of the technical solution, the processing device provided by the present invention can remove particles falling on the upper surface of the wafer before and after a process, so that partial etching defects can be overcome, thereby improving product yield.
Brief Description of Drawings
FIG. 1 is a structural section view according to an embodiment of the present LU101043 invention; and FIG. 2 is a front view of gas outlet ends of a gas pipeline according to an embodiment of the present invention.
Description of Embodiments Embodiments of the present invention are described in detail below by combination with accompanying drawings, but the present invention can be implemented by multiple different modes limited and covered by the claims.
The embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the present invention can be embodied in various different ways as defined and covered by the claims.
As shown in FIG. 1, a semiconductor shallow trench isolation etching processing device provided by an embodiment of the present invention includes a reaction chamber 100, a reaction gas pipe and a purger, where a chuck 11 for fixing a wafer 12 is arranged in the reaction chamber 100, and the chuck 11 is electrically connected with a bias power supply 22. The chuck 11 may be an electrostatic chuck or a mechanical chuck or the like. Further, a coil 23 is disposed above a top dielectric window 101 of the reaction chamber 100, and is electrically connected to an excitation power supply 25. Further, the top dielectric window 101 of the reaction chamber 100 is further provided with a central nozzle 24, and the reaction gas pipe conveys reaction gas into the reaction chamber 100 through the central nozzle 24. When a process is performed, the reaction gas is introduced into the reaction chamber 100 by the reaction gas pipe, and the excitation power supply 25 is turned on to load the coil 23 with radio frequency power, thereby exciting the reaction gas in the reaction chamber 100 to form a plasma, and the bias power supply 22 applies a bias voltage to the wafer 12 to attract the plasma to make the plasma move toward the wafer surface and etch the wafer surface.
The purger includes a gas pipeline and a gas source 21, where the gas source 21 is configured to supply a purge gas to the gas pipeline, and the purge gas isnitrogen or an inert gas such as argon, helium or the like, and does not react with 4101043 the reaction gas.
The gas pipeline is disposed in a chamber wall of the reaction chamber 100; a gas inlet end 20 of the gas pipeline is connected with the gas source 21, and gas outlet ends 19 of the gas pipeline are disposed on a chamber side wall 10 of the reaction chamber 100 and configured to convey the purse gas towards the upper surface of the wafer 12 and in the direction parallel to the upper surface of the wafer 12. Before and after the process is implemented, the upper surface of the wafer 12 is purged laterally (in a direction parallel to the upper surface of the wafer) by means of the above-mentioned purger to remove particles falling on the upper surface of the wafer, so that partial etching defects can be overcome, thereby improving product yield.
The gas pipeline includes a first branch 13 and a second branch 14; the first branch 13 and the second branch 14 are connected in parallel with each other, and are connected in series between the gas inlet end 20 and the gas outlet ends 19; the first branch 13 is provided with a first switching valve 15 and a first flow valve 17, and the first switching valve 15 is configured to open or close the first branch 13; the first flow valve 17 is configured to adjust a gas flow of the first branch 13; a second switching valve 16 and a second flow valve 18 are disposed on the second branch 14, and the second switching valve 16 is configured to open or close the second branch 14; and the second flow valve 18 is configured to adjust a gas flow of the second branch 14. The above-mentioned switching valve may be an oscillating valve or a butterfly valve or the like.
The flow valve may be a mass flowmeter (MFC), a throttle valve or a speed contro! valve or the like.
After the chuck 11 fixes the wafer 12, for example, when the chuck 11 is an electrostatic chuck, the chuck 11 is configured to stably fix the wafer 12 by electrostatic adsorption.
Before the process is implemented, the first switching valve 15 is connected with the first branch 13, and the second switching valve 16 opens the second branch 14; at the same time, the first flow valve 17 adjusts the gas flow of the first branch 13 to a first preset value, and the first preset value can be set according to specific conditions, as long as conveyed purge gas can removeparticles on the upper surface of the wafer 12; moreover, since the wafer 12 is LU101043 electrostatically adsorbed, even if a large gas flow is adopted, the position of the wafer 12 is not shifted, and thus particles with a large size can be blown off; these particles are pumped away through a pumping system, so that the upper surface of 5 the wafer 12 can be kept clean, and partial etching defects are effectively avoided, thereby improving product yield.
The value range of the aforementioned first preset : value is 500-1000 sccm, and preferably 800 sccm.
After the process is completed and the chuck 11 releases the fixation of the wafer 12, for example, the electrostatic chuck releases the electrostatic adsorption of the wafer 12, at this time the first switching valve 15 opens the first branch 13 and the second switching valve 16 closes the second branch 14; and at the time, the second flow valve 18 adjusts the gas flow of the second branch 14 to a second preset value.
Since the chuck 11 has released the fixation of the wafer 12, the aforementioned second preset value should be a smaller value to ensure that the position of the wafer 12 does not shift and does not affect the subsequent wafer taking operation.
The value of the second preset value ranges from 200 sccm to 500 sccm, and preferably 300 sccm.
In practical applications, a microprocessor can automatically control the operations of the first switching valve 15, the first flow valve 17, the second switching valve 16, and the second flow valve 18 described above, and can perform real-time adjustment of gas flows of the first flow valve 17 and/or the second flow valve 18 respectively or independently adjusts the gas flow of the first branch 13 and/or the second branch 14 according to specific purge conditions.
As shown in FIG. 3, the number of the gas outlet ends 19 of the gas pipeline is a plurality, and the gas outlet ends 19 are distributed at intervals along a chamber side wall 10 of the reaction chamber 100; and the heights of the gas outlet ends relative to the upper surface of the wafer 12 are the same, so that the density of gas flow entering the reaction chamber 100 can be increased, and thus the purge range can cover each area of the upper surface of the wafer 12. In practical applications, the number of the gas outlet ends can be set according to the diameter of the wafer
12 and the precision of a process. Preferably, the number of the gas outlet ends is 3 0101048 to 10. Of course, in practical applications, the number of gas outlet ends of the gas pipeline may also be one.
In addition, the horizontal spacing between the gas outlet ends 19 and an edge of the wafer 12 placed on the chuck 11 ranges from 0.5 cm to 5 cm to ensure a purging effect. The horizontal spacing is preferably 1 cm.
It should be noted that, in practical applications, the gas outlet ends of the gas pipeline can be disposed at any position on the chamber side wall, as long as the purging effect can be ensured. If the chamber side wall is provided with a dielectric window, the gas outlet ends can also be integrated on the dielectric window. Further, the manner in which the gas pipeline is disposed in the chamber wall of the reaction chamber is not limited to the manner employed in this embodiment, and the present invention has no limitation on this.
It should be further noted that the reaction gas pipe conveys the reaction gas into the reaction chamber 100 through the central nozzle 24. However, the present invention is not limited thereto, and in practical applications, the reaction gas may also be conveyed by any other intake means. For example, a plurality of edge nozzles may be added at a position close to the edge of the top dielectric window on the basis of the central nozzle, and the edge nozzles are symmetrically distributed with respect to the central nozzle. The reaction gas pipe uniformly conveys the reaction gas from the top of the reaction chamber to the inside through the edge nozzles. For another example, a plurality of nozzles may also be disposed on the chamber side wall of the reaction chamber, and uniformly distributed along the circumferential direction of the chamber side wall, and the reaction gas pipe uniformly conveys the reaction gas from the periphery of the reaction chamber to the inside through the respective nozzles.
The above are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and the equivalent structure or equivalent process transformations made by using the content of the specification and the accompanying drawings of the present invention may be
; ur . ; ; . . LU101043 directiy or indirectly applied to other related technical fields, and shall be included in a similar way in the scope of patent protection of the present invention.
Claims (4)
1. A semiconductor shallow trench isolation etching processing device, comprising a reaction chamber, a reaction gas pipe and a purger, wherein a chuck for fixing a wafer is arranged in the reaction chamber; and the reaction gas pipe is configured to convey reaction gas into the reaction chamber; wherein the processing device further comprises a purger, and the purger comprises a gas pipeline and a gas source; the gas source is configured to supply a purge gas to the gas pipeline, and the gas pipeline is disposed in a chamber wall of the reaction chamber; a gas inlet end of the gas pipeline is connected with the gas source, and gas outlet ends of the gas pipeline are disposed on a chamber side wall of the reaction chamber and configured to convey purse gas towards the upper surface of the wafer and in the direction parallel to the upper surface of the wafer.
2. The processing device according to claim 1, wherein the number of the gas outlet ends of the gas pipeline is a plurality, and the gas outlet ends are divided into one or more gas outlet groups; the multiple gas outlet groups are distributed at intervals in the direction perpendicular to the upper surface of the wafer; the plurality of gas outlet ends in the gas outlet groups are distributed at intervals along the chamber side wall of the reaction chamber, and the heights of the gas outlet ends relative to the upper surface of the wafer are the same.
3. The processing device according to claim 1, wherein the gas pipeline comprises a first branch and a second branch; the first branch and the second branch are connected in parallel with each other, and are connected in series between the gas inlet end and the gas outlet ends; the first branch is provided with a first switching valve and a first flow valve, and the first switching valve is configured to open or close the first branch; the first flow valve is configured to adjust a gas flow of the first branch; a second switching valve and a second flow valve are disposed on the second branch, and the second switching valve is configured to open or close the second branch; and the second flow valve is configured to adjust a gas flow of the second branch.
4. The processing device according to claim 1, wherein the purge gas LU101043 comprises nitrogen or an inert gas. | |
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| LU101043A LU101043B1 (en) | 2018-12-14 | 2018-12-14 | Semiconductor shallow trench isolation etching processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| LU101043A LU101043B1 (en) | 2018-12-14 | 2018-12-14 | Semiconductor shallow trench isolation etching processing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| LU101043B1 true LU101043B1 (en) | 2020-06-15 |
Family
ID=71090979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| LU101043A LU101043B1 (en) | 2018-12-14 | 2018-12-14 | Semiconductor shallow trench isolation etching processing device |
Country Status (1)
| Country | Link |
|---|---|
| LU (1) | LU101043B1 (en) |
-
2018
- 2018-12-14 LU LU101043A patent/LU101043B1/en active IP Right Grant
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| Date | Code | Title | Description |
|---|---|---|---|
| FG | Patent granted |
Effective date: 20200615 |