KR980700603A - MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPOERANDS - Google Patents

MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPOERANDS

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Publication number
KR980700603A
KR980700603A KR1019970703683A KR19970703683A KR980700603A KR 980700603 A KR980700603 A KR 980700603A KR 1019970703683 A KR1019970703683 A KR 1019970703683A KR 19970703683 A KR19970703683 A KR 19970703683A KR 980700603 A KR980700603 A KR 980700603A
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KR
South Korea
Prior art keywords
pack
data
processor
register
pack data
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Application number
KR1019970703683A
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Korean (ko)
Inventor
알렉산더 페레그
야아코프 야아리
밀린드 밋탈
래리 엠. 멘네마이어
베니 에이튼
Original Assignee
카알 실버맨
인텔 코퍼레이션
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Application filed by 카알 실버맨, 인텔 코퍼레이션 filed Critical 카알 실버맨
Publication of KR980700603A publication Critical patent/KR980700603A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
    • G06F7/20—Comparing separate sets of record carriers arranged in the same sequence to determine whether at least some of the data in one set is identical with that in the other set or sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

프로세서는 제어 신호(207)를 수신할 수 있도록 구성되는 디코더(202)를 포함한다. 상기 제어 신호는 제1소스 어드레스(602), 제2소스 어드레스(603), 목적 어드레스(605), 및 연산 필드(601)를 가진다. 상기 제1소스 어드레스는 제1위치와 일치하고, 상기 제2소스 어드레스는 제2위치와 일치한다. 상기 목적 어드레스는 제3위치와 일치한다. 상기 연산 필드는 팩 타입 데이터의 비교 연산이 수행될 것인지를 표시한다. 상기 프로세서는 상기 제1위치에 저장되는 제1팩 데이터와 상기 제2위치에 저장되는 제2팩 데이터를 비교하고 해당되는 결과 팩 데이터를 제3위치로 전달할 수 있도록 상기 디코더에 결합되어 구성되는 회로를 포함한다.The processor includes a decoder 202 configured to receive a control signal 207 . The control signal has a first source address 602 , a second source address 603 , a destination address 605 , and an operation field 601 . The first source address matches the first location, and the second source address matches the second location. The destination address coincides with the third location. The operation field indicates whether a comparison operation of pack type data is to be performed. the processor is a circuit coupled to the decoder to compare the first pack data stored in the first location with the second pack data stored in the second location and deliver the corresponding result pack data to the third location includes

Description

복합 피연산자의 비교 연산을 수행하는 마이크로프로세서(MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPERANDS)MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPERANDS

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this content is a publicly disclosed case, the full text is not included.

제2도는 본 발명 프로세서의 실시예를 나타낸 도면.Figure 2 shows an embodiment of the processor of the present invention;

Claims (15)

제어 신호를 수신할 수 있도록 구성되는 디코더로서, 상기 제어 신호는 제1위치와 일치하는 제1소스 어드레스, 제2위치와 일치하는 제2소스 어드레스, 제3위치와 일치하는 목적 어드레스, 및 팩 타입 데이터의 시프트 연산이 수행될 것인지를 표시하는 연산 필드를 가지는 디코더; 상기 디코더에 결합되는 회로로서, 상기 제1위치에 저장되는 제1팩 데이터와 상기 제2위치에 저장되는 제2팩 데이터를 비교하고, 해당되는 결과 팩 데이터를 제3위치로 전달하는 회로를 포함하여 구성되는 것을 특징으로 하는 프로세서.A decoder configured to receive a control signal, the control signal comprising a first source address matching a first location, a second source address matching a second location, a destination address matching a third location, and a pack type a decoder having an operation field indicating whether a shift operation of data is to be performed; A circuit coupled to the decoder, comprising a circuit for comparing the first pack data stored in the first position with the second pack data stored in the second position, and transferring the corresponding result pack data to a third position A processor, characterized in that it is configured. 제 1 항에 있어서, 상기 제1팩 데이터를 다수의 데이터 요소를 포함하고, 상기 다수의 데이터 요소의 각각의 데이터 요소는 크기를 가지며, 상기 연산 필드는 상기 크기에 대응되는 표시기를 더 포함하는 것을 특징으로 하는 프로세서.2. The method of claim 1, wherein the first pack data comprises a plurality of data elements, each data element of the plurality of data elements has a size, and wherein the operation field further comprises an indicator corresponding to the size. Characterized by the processor. 제 2 항에 있어서, 상기 크기는 팩 바이트, 팩 워드, 및 팩 더블워드 중의 하나인 것을 특징으로 하는 프로세서.3. The processor of claim 2, wherein the size is one of a pack byte, a pack word, and a pack doubleword. 제 2 항에 있어서, 상기 제1팩 데이터는 64비트인 것을 특징으로 하는 프로세서.3. The processor of claim 2, wherein the first pack data is 64 bits. 제 1 항에 있어서, 상기 목적 어드레스가 상기 제1소스 어드레스인 것을 특징으로 하는 프로세서.2. The processor of claim 1, wherein the destination address is the first source address. 제 1 항에 있어서, 상기 연산 필드는 상기 비교가 부호없는 상태로 수행될 것인지 부호있는 상태로 수행될 것인지를 판단하는 부호 표시기를 포함하는 것을 특징으로 하는 프로세서.2. The processor of claim 1, wherein the operation field includes a sign indicator for determining whether the comparison is to be performed unsigned or signed. 제 1 항에 있어서, 상기 팩 타입 데이터의 비교 연산은 동등한 것에 대한 비교 및 더 큰 것에 대한 비교 중 하나인 것을 특징으로 하는 프로세서.2. The processor of claim 1, wherein the comparison operation of the pack type data is one of a comparison for equal and a comparison for greater. 제 1 항에 있어서, 상기 프로세서는 레지스터를 포함하는 레지스터 파일을 포함하고, 상기 제2위치가 상기 레지스터와 일치하는 것을 특징으로 하는 프로세서.2. The processor of claim 1, wherein the processor includes a register file containing registers, and wherein the second location coincides with the register. 제 8 항에 있어서, 상기 제1위치는 메모리 위치와 일치하는 것을 특징으로 하는 프로세서.9. The processor of claim 8, wherein the first location coincides with a memory location. 디코더, 기능 유닛, 제1레지스터 및 제2레지스터를 구비하는 프로세서로, 상기 디코더는 상기 기능 유닛, 상기 제1레지스터 및 상기 제2레지스터와 결합되도록 구성되는 프로세서 내의 팩 데이터를 비교하는 방법에 있어서, 상기 디코더가 제어 신호를 디코딩하는 단계; 상기 제1레지스터에 저장된 제1팩 데이터를 억세스하는 단계; 상기 제2레지스터에 저장된 제2팩 데이터를 억세스하는 단계; 상기 제어 신호를 디코딩하는 상기 디코더에 반응하여, 상기 기능 유닛이 상기 제1팩 데이터와 상기 제2팩 데이터를 비교하고 결과 팩 데이터를 발생시키는 단계; 상기 결과 팩 데이터를 상기 제1레지스터에 저장하는 단계를 포함하여 이루어지는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.A method for comparing pack data in a processor comprising a decoder, a functional unit, a first register and a second register, the decoder configured to be combined with the functional unit, the first register and the second register, the method comprising: decoding, by the decoder, a control signal; accessing first pack data stored in the first register; accessing second pack data stored in the second register; in response to the decoder decoding the control signal, the functional unit comparing the first pack data and the second pack data and generating result pack data; and storing the result pack data in the first register. 제 10 항에 있어서, 상기 제어 신호는 그룹으로 부터의 비교 연산이 동등, 및 더 큰 경우에는 1을 표시하는 비교 타입 표시기를 포함하는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.11. The method of claim 10, wherein the control signal includes a comparison type indicator indicating that the comparison operation from the group is equal, and 1 if greater. 제 10 항에 있어서, 상기 제1팩 데이터는 다수의 데이터 요소를 포함하고, 상기 다수의 데이터 요소의 각 데이터 요소는 미리결정된 비트 수를 표현하며, 상기 제어 신호는 상기 미리결정된 비트 수를 표시하는 크기 표시기를 포함하는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.11. The method of claim 10, wherein the first pack data comprises a plurality of data elements, each data element of the plurality of data elements represents a predetermined number of bits, and wherein the control signal indicates the predetermined number of bits. A method of comparing pack data within a processor comprising a size indicator. 제 10 항에 있어서, 상기 제1레지스터는 64비트의 길이이고, 상기 제1팩 데이터는 8개의 팩 바이트 데이터 요소를 포함하는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.11. The method of claim 10, wherein the first register is 64 bits long and the first pack data contains eight packed byte data elements. 제 10 항에 있어서, 상기 비교는 상기 제2팩 데이터로부터 상기 제1팩 데이터는 빼는 단계 및 상기 뺄셈의 결과를 테스트하는 단계를 포함하는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.11. The method of claim 10, wherein the comparing comprises subtracting the first pack data from the second pack data and testing the result of the subtraction. 제 10 항에 있어서, 상기 결과 팩 데이터는 다수의 결과 데이터 요소를 포함하고, 상기 비교는 상기 다수의 각 데이터 요소의 각 데이터 요소를 모두 1 또는 모두 0으로 하는 것을 특징으로 하는 프로세서 내의 팩 데이터를 비교하는 방법.11. The method of claim 10, wherein the result pack data comprises a plurality of result data elements, and wherein the comparison equals each data element of each data element to all ones or all zeros. How to compare. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed according to the contents of the initial application.
KR1019970703683A 1994-12-02 1995-12-01 MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPOERANDS KR980700603A (en)

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US34904094A 1994-12-02 1994-12-02
US08/349,040 1994-12-02

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AU4507396A (en) 1996-06-19

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