KR960011683A - Microprocessors that execute instructions with operand fields, including parts used as part of opcode - Google Patents

Microprocessors that execute instructions with operand fields, including parts used as part of opcode Download PDF

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Publication number
KR960011683A
KR960011683A KR1019950031739A KR19950031739A KR960011683A KR 960011683 A KR960011683 A KR 960011683A KR 1019950031739 A KR1019950031739 A KR 1019950031739A KR 19950031739 A KR19950031739 A KR 19950031739A KR 960011683 A KR960011683 A KR 960011683A
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South Korea
Prior art keywords
instruction
field
response
operand
operand field
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KR1019950031739A
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Korean (ko)
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KR100229056B1 (en
Inventor
다카시 나카야마
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가네코 히사시
닛본 덴기 가부시끼가이샤
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Publication of KR960011683A publication Critical patent/KR960011683A/en
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Publication of KR100229056B1 publication Critical patent/KR100229056B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

마이크로프로세서는 실행되는 명령어에 관하여 1-바이트 유닛, 2-바이트 유닛, 4-바이트 유닛 등의 메모리 및 레지스터 간에 데이타를 전달하기 위해 각각의 LOAD 또는 STORE 명령을 실행하도록 구성된다. 이들 명령에 있어서, 연산 필드의 서로 동일한 내용을 갖는 명령으로 제공된다. 실행되는 명령을 판별하기 위해 실행 유닛에 대하여, 연산 필드 뿐만 아니라 오퍼랜드 필드의 일부도 사용된다.The microprocessor is configured to execute respective LOAD or STORE instructions to transfer data between memory and registers, such as 1-byte units, 2-byte units, 4-byte units, etc., with respect to the instructions being executed. In these instructions, they are provided as instructions having the same contents of the operation fields. For the execution unit, not only the operation field but also part of the operand field is used to determine the instruction to be executed.

Description

연산 코드의 일부로 사용되는 부분을 포함한 오퍼랜드 필드를 갖는 명령어를 실행하는 마이크로프로세서Microprocessors that execute instructions with operand fields, including parts used as part of opcode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 따른 마이크로프로세서를 예시하는 블록도,2 is a block diagram illustrating a microprocessor in accordance with an embodiment of the present invention;

제3도는 제2도에 도시된 마이크로 프로세서에 의해 실행되는 LOAD 또는 STORE 명령의 명령어 포맷 표시도,3 is a diagram showing the instruction format of the LOAD or STORE instruction executed by the microprocessor shown in FIG.

제4도는 제2도에 도시된 마스크 회로를 예시하는 회로도.4 is a circuit diagram illustrating the mask circuit shown in FIG.

Claims (5)

명령어 스트림의 각각을 수신 및 실행하는 실행 수단을 구비하는데, 상기 명령어 스트림은 제1 및 제2명령어를 포함하며, 각각의 상기 명령어 스트림은 연산 필드 및 오퍼랜드 필드를 가지고, 상기 실행 수단은 상기 제1명령어의 상기 연산 필드에 단지 응답하여 상기 제1명령어에 의해 요구되는 데이타 처리 연산을 판별하며, 상기 제2명령어의 상기 연산 필드 및 상기 제2명령어의 상기 오퍼랜드 필드 일부에 응답하여 상기 제2명령어에 의해 요구되는 데이타 처리 연산을 판별하는 것을 특징으로 하는 마이크로프로세서.Execution means for receiving and executing each of the instruction streams, wherein the instruction stream comprises first and second instructions, each of the instruction streams having an operation field and an operand field, and the execution means having the first Determine a data processing operation required by the first instruction only in response to the operation field of the instruction, and respond to the second instruction in response to a portion of the operation field of the second instruction and the operand field of the second instruction. Microprocessor to determine the data processing operations required by the processor. 제1항에 있어서, 상기 제1 및 제2명령어의 각각은 레지스터 및 메모리간의 데이타 전송을 수행하도록 상기 실행 수단에게 명령하며, 상기 실행 수단은 상기 제1명령어에 응답하여 제1바이트 수에 의해 또한 상기 제2명령어에 응답하여 제1바이트 수에 의해 상기 데이타 전송을 수행하며, 상기 제1바이트 수는 상기 제2바이트 수와 다른 것을 특징으로 하는 마이크로프로세서.2. The apparatus of claim 1, wherein each of the first and second instructions instructs the execution means to perform data transfer between a register and a memory, wherein the execution means is further defined by the first byte number in response to the first instruction. And perform the data transfer by a first byte number in response to the second instruction word, wherein the first byte number is different from the second byte number. 제2항에 있어서, 상기 제1 및 제2명령어의 각각에 대한 상기 오퍼랜드 필드를 상기 메모리의 주소를 지정하는데 사용되는 오프셋 데이타를 가리키는 오프셋 필드부를 포함하며, 상기 오퍼랜드 필드의 상기 일부는 상기 오프셋 필드부에 포함되어 있는 것을 특징으로 하는 마이크로프로세서.3. The method of claim 2, further comprising: an offset field portion indicating offset data used to address said operand field for each of said first and second instructions, said portion of said operand field being said offset field. Microprocessors included in the part. 연산 필드 및 오퍼랜드 필드를 포함하는 실행될 명령어를 일시적으로 기억하는 기억 수단과, 상기 연산 필드 및 상기 명령어의 상기 오퍼랜드 필드의 일부를 수신하도록 상기 기억 수단에 결합되며, 상기 연산 필드에 응답하여 디코드된 정보를 발생하도록 제1모드에서 동작하고 상기 연산 필드 및 상기 오퍼랜드 필드의 상기 일부에 응답하여 디코드된 정보를 발생하도록 제2모드에서 동작하는 디코더 및 상기 디코더로부터 디코드된 정보를 수신하도록 결합되고 그에 응답하여 상기 명령어를 실행하는 실행 유닛을 구비하는 것을 특징으로 하는 마이크로프로세서.Storage means for temporarily storing an instruction to be executed comprising an operation field and an operand field, and information coupled to the storage means to receive the operation field and a portion of the operand field of the instruction and decoded in response to the operation field A decoder operating in a second mode to generate decoded information in response to the portion of the operation field and the operand field to generate a decoded information and receiving decoded information from the decoder in response thereto; And an execution unit for executing the instruction. 제4항에 있어서, 상기 오퍼랜드 필드의 상기 일부를 수신하고, 상기 오퍼랜드 필드의 상기 일부를 출력하도록 상기 제1모드에서 동작하며 소정의 데이타를 출력하도록 상기 제2모드에서 동작하는 제어 회로와, 상기 오퍼랜드 필드의 남아 있는 부분과 상기 제어 회로의 출력 데이타에 응답하여 액세스 어드레스를 발생하는 어드레스 계산 유닛을 구비하는 것을 특징으로 하는 마이크로프로세서.5. The apparatus of claim 4, further comprising: a control circuit operating in the second mode to receive the portion of the operand field and to output the portion of the operand field and to output predetermined data; And an address calculation unit for generating an access address in response to the remaining portion of the operand field and the output data of the control circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031739A 1994-09-20 1995-09-20 Microprocessor executing instruction having operand field including portion used as part of operation code KR100229056B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6250148A JP2682469B2 (en) 1994-09-20 1994-09-20 Instruction code encoding method
JP94-250148 1994-09-20

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KR100229056B1 KR100229056B1 (en) 1999-11-01

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EP0703529B1 (en) 1998-06-17
KR100229056B1 (en) 1999-11-01
DE69503010D1 (en) 1998-07-23
EP0703529A1 (en) 1996-03-27
US5922067A (en) 1999-07-13
DE69503010T2 (en) 1999-02-18
JPH0895780A (en) 1996-04-12
JP2682469B2 (en) 1997-11-26

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