JPS6488826A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6488826A
JPS6488826A JP62246621A JP24662187A JPS6488826A JP S6488826 A JPS6488826 A JP S6488826A JP 62246621 A JP62246621 A JP 62246621A JP 24662187 A JP24662187 A JP 24662187A JP S6488826 A JPS6488826 A JP S6488826A
Authority
JP
Japan
Prior art keywords
instruction
memory
data
register
byte length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62246621A
Other languages
Japanese (ja)
Other versions
JP3041308B2 (en
Inventor
Takeshi Sakamura
Toyohiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62246621A priority Critical patent/JP3041308B2/en
Publication of JPS6488826A publication Critical patent/JPS6488826A/en
Priority to US07/631,197 priority patent/US5132898A/en
Application granted granted Critical
Publication of JP3041308B2 publication Critical patent/JP3041308B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To execute the arithmetic operation between binary numbers different in data size stored in two registers without arithmetic shift by storing to the register the data having a shorter byte length than the byte length of the register by justifying the the lowest-order bit to the data having the same byte length on the other register. CONSTITUTION:The instruction from an instruction fetch part 1 is inputted to a memory 10 through an address bus 8, and the instruction selected in the memory is returned to the fetch part 1, and the instruction from the part 1 is sent to an instruction decoding part 2, and obtained information like a microprogram entry address is stored in a micro RAM 7 and is applied to an instruction execution control part 3. Simultaneously, this information is counted by a microprogram counter 6, and an instruction executing part 5 is operated to input information to the memory 10 through an operand access part 4, and the calculated operation result from the memory 10 is outputted from a data bus 9.
JP62246621A 1987-09-30 1987-09-30 Data processing device Expired - Fee Related JP3041308B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62246621A JP3041308B2 (en) 1987-09-30 1987-09-30 Data processing device
US07/631,197 US5132898A (en) 1987-09-30 1990-12-20 System for processing data having different formats

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246621A JP3041308B2 (en) 1987-09-30 1987-09-30 Data processing device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP9261556A Division JP2878250B2 (en) 1997-09-26 1997-09-26 Data processing device
JP24169599A Division JP3643270B2 (en) 1999-08-27 1999-08-27 Data processing device

Publications (2)

Publication Number Publication Date
JPS6488826A true JPS6488826A (en) 1989-04-03
JP3041308B2 JP3041308B2 (en) 2000-05-15

Family

ID=17151130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246621A Expired - Fee Related JP3041308B2 (en) 1987-09-30 1987-09-30 Data processing device

Country Status (1)

Country Link
JP (1) JP3041308B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881654U (en) * 1981-11-24 1983-06-02 株式会社日立製作所 arithmetic processing unit
JPS61169934A (en) * 1985-01-23 1986-07-31 Nec Corp Method for storing arithmetic result of bit row data in register
JPS61223939A (en) * 1985-03-29 1986-10-04 Canon Inc Arithmetic and logical unit
JPS62184530A (en) * 1986-02-06 1987-08-12 エムアイピ−エス　コンピユ−タ−　システムズ、インコ−ポレイテイド Computer architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881654U (en) * 1981-11-24 1983-06-02 株式会社日立製作所 arithmetic processing unit
JPS61169934A (en) * 1985-01-23 1986-07-31 Nec Corp Method for storing arithmetic result of bit row data in register
JPS61223939A (en) * 1985-03-29 1986-10-04 Canon Inc Arithmetic and logical unit
JPS62184530A (en) * 1986-02-06 1987-08-12 エムアイピ−エス　コンピユ−タ−　システムズ、インコ−ポレイテイド Computer architecture

Also Published As

Publication number Publication date
JP3041308B2 (en) 2000-05-15

Similar Documents

Publication Publication Date Title
US4228498A (en) Multibus processor for increasing execution speed using a pipeline effect
US4463421A (en) Serial/parallel input/output bus for microprocessor system
US4680701A (en) Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4403284A (en) Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address
US4402042A (en) Microprocessor system with instruction pre-fetch
US4694391A (en) Compressed control decoder for microprocessor system
KR950033803A (en) Multiple bit shift device, data processor using same, and multiple bit shift method
US4402044A (en) Microprocessor with strip layout of busses, ALU and registers
KR910010301A (en) Command designation method and execution device
US4539635A (en) Pipelined digital processor arranged for conditional operation
KR930018378A (en) Method and device for performance optimization of cache memory system
KR940015852A (en) Handler with long instruction word
GB1426748A (en) Small micro-programme data processing system employing multi- syllable micro instructions
US4402043A (en) Microprocessor with compressed control ROM
EP0913764B1 (en) Method and apparatus for shifting data
US4093983A (en) Fast and normal rate instruction fetching
KR930008605A (en) Programmable controller
JPS6212529B2 (en)
JPH034936B2 (en)
TW325552B (en) Data processing condition code flags
GB1179048A (en) Data Processor with Improved Apparatus for Instruction Modification
JPS6488826A (en) Data processor
JPH0345420B2 (en)
US4723258A (en) Counter circuit
JP2567134B2 (en) Bit field logical operation processing device and monolithic microprocessor having the same

Legal Events

Date Code Title Description
S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313115

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees