JPS61223939A - Arithmetic and logical unit - Google Patents

Abstract

PURPOSE:To execute a data processing at a high speed by generating newly an instruction for reversing the sequence of a bit train. CONSTITUTION:An instruction of a bit train reverse sequence instruction which has been generated newly is formed by an OP code 20, an operand part 21 for indicating an address in a memory 12 in which a data which is to be brought to reverse sequence has been stored, and an operand 22 for showing the number of words of a data which is to be brought to reverse sequence. In this state, when the execution of a program advances, and it is detected by an instruction decoder 6 to be the bit train reverse sequency instruction, it is brought to an execution processing by one instruction by utilizing said instruction code.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application in LM Business The present invention relates to a logical arithmetic device for data processing that decodes and executes instructions.

Summary of the Disclosure This specification and the drawings disclose a technique for performing high-speed data processing by decoding and executing an instruction to reverse the order of the bits forming data in a logical arithmetic unit.

2. Description of the Related Art In the process of processing data by a logical arithmetic unit forming a data processing system, it is often necessary to reverse the order of the bits forming the data.

However, conventional logical arithmetic units do not have an instruction to reverse the bit string, so when reversing the bit string, 1
It is necessary to take out each bit one by one and arrange them in reverse order, which has the disadvantage of slow processing speed.

Furthermore, there is a problem in creating a program that a program must be created by repeating a plurality of instructions.

E. Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides a logic arithmetic device that can reverse the order of bit positions constituting data by a single instruction.

Means for solving the problem
0 is connected to the storage device 101 and is a logical operation unit! 1
100 is an instruction decoding unit 102 and a bit string reverse order processing unit 103
It has

1 action” In the above configuration, the instruction decoding unit 102
Read and decipher the instructions. If the read instruction is an instruction to reverse bit order, the bit string reverse order processing unit 103 reads data from the storage device 101 and reverses each bit making up the read data.

[Embodiment] FIG. 2 is a more specific embodiment of the embodiment shown in FIG. below,
GR), 2 is an arithmetic logic unit (hereinafter referred to as ALU),
3 is stored in the control memory 15, which will be described later, and shown in FIGS.
); 4 is a program counter (hereinafter referred to as PC); s;
is an instruction register (hereinafter referred to as IR), 6 is an instruction decoder (hereinafter referred to as 10) that analyzes IR5, 7 is a memory address register (hereinafter referred to as MAR), 8 is a memory data register (hereinafter referred to as IR), 9 is a bit string reverse order circuit, lO is an internal bus, and 11 is a memory control circuit (hereinafter referred to as MC).
), 12 is a memory (hereinafter referred to as MEMORY).

FIG. 3 is a detailed diagram of the control circuit 3. The control circuit 3 of this embodiment uses microprogram control, and 13 is a microprocessor (hereinafter referred to as CPυ), and 15 is a control for storing the microprogram. Memory (hereinafter referred to as C9), 1
Reference numeral 4 denotes a control bus interface for exchanging control information with various components within the logical arithmetic unit 100.

FIG. 4 is a format diagram of an example of an instruction for reversing a bit string. 20 is an instruction code (hereinafter referred to as 0P-COD) representing the type of instruction; 21 is an operand (hereinafter referred to as A-ADDRESS) indicating the address in MENORYZ where data to be reversed is stored; and 22 is an instruction code to be reversed. The operand (hereinafter referred to as 1 word number) representing the number of words of exponent data is 0. In this embodiment, in order to simplify the explanation, it is assumed that one word is composed of 8 bits.

FIG. 5 shows how the bits of the 8-bit data are reversed according to this embodiment. In the figure, b7 to bo represent signal positions, and V7 to VO represent binary data values.

Figure 146 shows the relationship between the bit string reverse order circuit 9 and the old R8.
7 to MRo, and A which is the output of the accumulator 31
CC Fu~ACG o. The select inputs of multiplexer 35 are -memory read °' and ACC + NIR''. 30 is also an 8-bit multiplexer, and one set of its inputs selects the input to accumulator 31.
The other sets of input signals are various data signals used within the logical operation device 100, and the old R8's crest f~bo, which is not shown here, is the input to the multiplexer 30. It should be noted that the terminals are in reverse order.The signal REV33 is sent to the multiplexer 30.
, the multiplexer 30 selects the set of inputs b o
"b7" is selected and inputted to the accumulator 31.The accumulator 31 receives the signal "NIR→Ace".
34 latches the output of multiplexer 30.

The data thus read from MEMORY I2 is stored in the accumulator 31 in reverse order via IR8. The reversed data is sent to ME again via MIR8.
It is stored in MORYI 2 or used within the logic operation unit 100 via the internal bus IO.

In addition, the tabs in the figure % u IJ -F ”ACC-+1ll
The signals ``IR'', ``MIR→AGO'', and ``REV''' are microoperators generated within the control circuit 3.

Next, the basic operation of the embodiment will be explained based on the flowcharts of FIGS. 7(a) and 7(b). This control procedure is a program stored in the C915 in the control circuit 3. An example of the instruction described below follows the instruction format shown in FIG. 3, and is to reverse the bit order of data read from MEMORY12 and store it in MEMORY12 again.

FIG. 7(a) is a flowchart of FETC) I CYCLE. 887 (a) is a flowchart of FETCHCYCLE of the logical operation device 100. First, in step 510, S12, the MEMOR specified by PO2 is
In step S14, the data of Y12 is read, and the read data is loaded into the IR5 via the MIR8.

If the instruction is an instruction other than the bit string reverse order instruction (
If NO in step 516), the process proceeds to step S22, where the command processing (EXECU'rE CYCLE) is performed, and in step 324, PO2 is set to an appropriate bias, and the process returns to step SIO.

If the determination in step S16 is YES, step S1
8, the bit string is processed in reverse order. Finish the process and advance PO2 by one in step 320.
Start FETCHCYCLE of another instruction again.

Figure 7 (b) (tEXEcUTE CYCLE
(F) It is an o-chart. MA in step S30
Set the contents of A-ADDRESS21 in R7.0 Next, in step S32, the memory is read, and a signal "-memory read" is sent to the multiplexer 35, and the I
Latch data into R8.

In step S34, the signals "REV" and "MIR+"
ACC°' is sent to the bit string route circuit 9, and the route data is latched into the accumulator 31. Step 336
Then, set the contents of A-ADDRESS 21 in MAR7 again, send the signal "ACC→MIR" in step 538, latch the data in MIR8, and proceed to step 5.
Then, in step S42, the word counter 32 is counted down by 1, and in step S4
4, A-ADDRESS 21 is counted up to address 1. The operations of steps 330 to S40 described above are repeated until the word counter 32 reaches ``''θ'' in step 346. In this way, the bits of the specified data in MEMORY 12 are reversed with one instruction.

In the above embodiment, an instruction for re-storing the data read from MEMORYl 2 in reverse bit order into MEMORYl 2 was given as an example, but other instructions include reversing the data in GRI and returning it to GRI again. Commands can also be considered.

As explained above, by adding an instruction to reverse the bit string, high-speed processing becomes possible when handling a large amount of bit strings, such as in image processing.

(Effects of the Invention) As described above, according to the present invention, the positions of constituent bits of data are reversed with a single instruction, so high-speed data processing is possible.

[Brief explanation of the drawing]

! ! FIG. 81 is a basic configuration diagram of the embodiment, FIG. 882 is a detailed configuration diagram of the embodiment, FIG. 3 is a configuration diagram of a control circuit, and FIG. 4 is an instruction format diagram according to an example. FIG. 5 is an explanatory diagram of the operation of the bit string route. FIG. 6 is a detailed diagram of the bit string reverse order circuit, and FIGS. 1117(a) and (b) are flowcharts of the control procedure of the embodiment. Patent applicant Canon Co., Ltd. Mei-1, -- Figure 1 Figure 7 (0)

Claims (1)

[Claims] In a logical arithmetic device that processes data and has an instruction decoding section and an instruction execution section, the instruction execution section performs bit reversal processing for reversing the positions of bits constituting data based on instructions from the instruction decoding section. A logic operation device characterized by having a section.