KR980012612A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The semiconductor device includes a semiconductor layer, a first insulator film formed on the semiconductor layer, first and second wiring conductors formed on the first insulator film having a space left therebetween, and a second insulator film buried in the space. And a second insulating film formed on the first insulating film. The second insulator film has a higher etch ratio than the first insulator film and a lower relative dielectric constant than the first insulator film. The second insulating film may be either a silicon oxide film to which fluorine is added or a fluorine-containing amorphous carbon film when the first insulating film is a silicon oxide film. In the semiconductor device manufacturing method, the first insulator film is formed on the semiconductor layer. The second insulator film is formed on the first insulator film. The first and second set portions of the second insulator film are selectively etched by using the first insulator film as an etch stopper to form the first and second wiring channels. The first and second wiring conductors are selectively formed in the first and second wiring channels.

Description

Semiconductor device and manufacturing method thereof

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method of forming a wiring layer having a low eddy current capacity by use of a buried wiring conductor (or buried metal line).

In traditional techniques, the wiring form is formed by etching the metal wiring material. However, traditional techniques have not been able to fully meet the recent demand for semiconductor devices having very good configurations because the accuracy of the wiring form is not sufficient due to the halation of the exposed metal wiring material.

In view of the above, a conventional method for forming a first wiring form using wiring trenches or channels has been proposed. In particular, the wiring channel is filled with a metal wiring material that is formed in the insulator film and provides a buried wire conductor (or buried metal line). Compared with the conventional method of etching the above-mentioned metal wiring material, it is an easy task to form a good channel in the form of wiring by etching the insulating film. In addition, a better configuration wiring form can be easily obtained by ensuring excellent flatness. Therefore, this method is very basic and useful for the fabrication of large-capacity integrated (LSI) circuits in the ongoing need to obtain a better appearance. The conventional first buried wiring conductor (or buried metal line) forming method is, for example, in Japanese Unexamined Patent Publication (JP-A) 6-244180 (244180/1994). Referring to FIG. 1, the method is depicted. As shown in the figure, the semiconductor substrate 50 has a source and drain region 101 ', a gate electrode 102' and a field oxide film 103 '. The first interlayer insulating film 51, the silicon nitride film 52, and the second interlayer insulating film 53 are successively stacked on the semiconductor substrate 50. The plurality of wiring channels 54 are formed through the second insulator film 53 and the silicon nitride film 52. In the above-described configuration, the first and second interlayer insulating films 51 and 53 typically include a silicon oxide film or a boron-doped phospho-silicate glass (BPSG) film. The silicon nitride film 53 has a low etch ratio and functions as an etch stopper film for unevenly suppressing the depth of the wiring channel 54. Therefore, the first conventional method requires an etch stopper film to be formed under the wiring channel in order to obtain a uniform channel depth.

In the meantime, the LSI circuit has encountered a serious problem in improving a semiconductor device having a very good configuration and densely arranged. In particular, the circuit delay was increased by the eddy current capacity and resistance of the wiring conductors or metal lines connecting the semiconductor devices to each other. As the distance between adjacent wiring conductors (or metal lines) was reduced, the eddy current capacity therebetween increased. This increases the occurrence of line delay and crosstalk. Therefore, the presence of the eddy current capacity makes it difficult to increase the operating speed of the LSI circuit and avoid operating errors.

In order to reduce the eddy current capacity between adjacent wiring conductors or metal lines, it is a common practice to use an insulating film having a low dielectric constant. Because of the insulator film having a low dielectric constant, various films with organic film such as fluorine-containing silicon oxide (SIOF) film and polytetrafluoro-ethylene film have been proposed. These films often contain fluorine and so cause corrosion of wiring conductors or metal lines. Moreover, these films did not provide metal-based adhesion and could not be arranged to make direct contact with the wiring conductors (or metal lines). Therefore, a silicon oxide film known in the art is used as a film in direct contact with a wiring conductor or a rapid line.

Referring to Fig. 2, a second conventional method of forming a multi-layered metal configuration by using an insulator film having a low dielectric constant will be described. The multi-layered metal configuration includes a substrate 60, a first silicon oxide film 61, a second silicon oxide film 62, a low dielectric film 63 having a low dielectric constant, a third silicon oxide film 64, Metal lines (wiring conductors) 65 and barrier metals 66.

In the first conventional method of forming a buried metal line having a silicon oxide film or a BPSG film used as the above-mentioned interlayer insulator film, the etch stopper film (silicon nitride film in the illustrated example) has a high relative dielectric constant. Therefore, as compared with the conventional technique of forming the wiring form by etching the metal wiring material, line delay and crosstalk occur due to the increased vortex capacity between adjacent metal lines. In view of the foregoing, the thickness of the silicon nitride film as a stopper must be reduced. As a result, when the wiring channel is formed by etching, the etching selection between the silicon oxide film and the silicon nitride film must be sufficiently high. In addition, the silicon nitride film is undesirably penetrated and cannot function sufficiently as an etch stopper film. As the degree of integration of the metal composition increases, the eddy current capacity between adjacent metal lines increases further under the greater influence of the silicon nitride film. Therefore, the silicon nitride film must be further reduced in thickness. Therefore, the first conventional method cannot be applied to the manufacture of the high direct circuit, which is expected for the next generation and the next generation. For example, it is assumed that the silicon nitride film as an etch stopper should have a thickness of 100 nm. As a result of this. Vortex capacity between adjacent metal lines is increased by about 10%.

The use of an insulator film having a low dielectric constant will be noted. According to the technical trend, the thickness of the interlayer insulating film is not reduced. Therefore, in the highly integrated circuit example, it is most important to reduce the vortex capacitance between adjacent metal lines rather than the vortex capacitance between the wiring layer and the substrate and between the wiring layers. Vortex capacitance between adjacent metal lines can be effectively suppressed by the presence of an insulating film having a low dielectric constant between adjacent metal lines. In other words, the insulator film having a low dielectric constant need not be formed as an overlaying layer on the wiring layer.

Referring to Fig. 3, the total line capacity (x10 ^-1 fF / mu m) that changes due to a decrease in line pitch is partitioned according to four different configurations (in solid lines in the figure).

(1) A nitride film having a thickness of 100 nm is formed below the wiring channel as an etch stopper film.

(2) A silicon oxide film is inserted between the metal lines.

(3) The SIOF film is inserted between the metal lines.

(4) A fluorine-containing amorphous carbon film is inserted between the metal lines.

Moreover, the eddy current capacity between the substrate and the wiring layer and between adjacent metal lines is also shown in dashed lines with respect to one of the configurations. In the figure, abscissa and ordinate represent line pitch and capacity, respectively. As can be understood from the figure, the vortex capacity between adjacent metal lines increases dramatically and accounts for a greater proportion of the total line capacity following the decrease in line pitch.

Accordingly, an object of the present invention is to provide a semiconductor device having a wiring conductor (or metal line) buried in a low-dielectric film having an effectively suppressed eddy current capacity.

Another object of the present invention is to provide a method for manufacturing a semiconductor device, which makes it possible to easily form a wiring conductor (or metal line) buried in a low-dielectric film and to effectively suppress the eddy current capacity between the wiring conductors.

According to one aspect of the present invention, there is provided a semiconductor layer comprising: a semiconductor layer; A first insulating film formed on the semiconductor layer; First and second wiring conductors formed on the first insulator film having a space left between them; And a second insulator film formed on the first insulator film having a second insulator film buried in the space. The second insulator film has a higher etch ratio than the first insulator film and a lower relative dielectric constant than the first insulator film.

Preferably, the second insulator film may be either a silicon oxide film to which fluorine is added or a fluorine-containing amorphous carbon film when the first insulator film is a silicon oxide film.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising a semiconductor layer, comprising: forming a first insulator film on the semiconductor layer; Forming a second insulator film having an etch ratio higher than the first insulator film and a relative dielectric constant lower than that of the first insulator film, on the first insulator film; Selectively etching the first and second set portions of the second insulator film by using the first insulator film as an etch stopper to form first and second wiring channels; And selectively forming first and second wiring conductors in the first and second wiring channels.

The second insulating film may be either a silicon oxide film to which fluorine is added or a fluorine-containing amorphous carbon film when the first insulating film is a silicon oxide film.

As described above, the semiconductor device and its manufacturing method according to the present invention belong to being used as an interlayer insulating film (first insulating film) between the first and the lower wiring layers. The interlayer insulating film under the low dielectric film functions as an etch stopper film. The second feature is that the wiring channel is filled with a metal conductor film formed in the low-dielectric film as the second insulator film.

Since the interlayer insulating film is sufficiently thick as the etch stopper film, a wiring channel of uniform thickness can be easily formed. Using a low-dielectric insulating film between metal lines effectively reduces the eddy current capacity.

1 is a cross-sectional view showing a conventional method of manufacturing a first semiconductor device having buried metal lines;

2 is a cross-sectional view showing a conventional second semiconductor device manufacturing method using a low dielectric film;

3 is a graph comparing the vortex capacity, which changes with an increase in line pitch,

4A to 4F show a semiconductor device manufacturing process according to the first embodiment of the present invention;

5A to 5F show a semiconductor device manufacturing process according to the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

12: SIOF film 13, 24: wiring channel

14, 25: contact hole 16: tin film

17 aluminum film 22 hydrogen-containing amorphous carbon film

23 fluorine-containing amorphous carbon film 50 substrate

51: first interlayer insulating film 52: silicon nitride film

53: second interlayer insulating film 54: wiring channel

101, 101 ': source and drain regions 102, 102': gate electrode

103, 103 ': field oxide

Several preferred embodiments of the present invention will now be described with reference to the drawings.

4A to 4F, a method of manufacturing a semiconductor device according to a first embodiment of the present invention is shown.

Referring first to FIG. 4A, the semiconductor substrate 10 has a device region including a MOS transistor. To be precise, the semiconductor substrate 10 has a source and drain region 101, a gate electrode 102, and a field silicon oxide film 103. The first silicon oxide film 11 is laminated on the semiconductor substrate 10 by plasma CVD with a thickness of 0.6 mu m. Then, the first silicon oxide film 11 is polished chemically and mechanically so as to be flattened. Here, the thickness of the first silicon oxide film 11 is adjusted to 0.5 占 퐉 in the field silicon oxide film 103. Thus, the SIOF film 12 is laminated on the flattened first silicon oxide film 11 to a thickness of 0.5 mu m by plasma CVD. For example, the lamination of the SIOF film 12 is performed by using the lamination gas of SiF4,02 and Ar supplied to the semi-finished chamber at flow ratios of 40 sccm, 80 sccm and 70 sccm, respectively. The reaction chamber is operated at RF power of 1.4 kW. As a result, the SIOF film 12 has a relative dielectric constant of 3.5.

Referring next to FIG. 4B, a channel shaped stop mask is formed on the SIOF film 12 by using a typical ore plate technique. Then, the SIOF film 12 is anisotropic dry etched to form the wiring channel 13. Dry etching is performed under conditions similar to the etching conditions of a typical silicon oxide film. For example, it operates at 1000 W of RF power maintained at a pressure of 300 mT in the reaction chamber, and is supplied with etching gases of Ar, CF ₄ and CHF ₃ at flow rates of 200 sccm, 20 sccm and 20 sccm, respectively. Under the above-described conditions, the SIOF film 12 can be etched-etched approximately three times that of the first silicon oxide film 11. Therefore, even if excessive etching is performed before the selected etch depth is calculated from the desired thickness of the SIOF film 12, the entire first silicon oxide film 11 acts as an etch stopper film to obtain a wiring channel 13 of uniform thickness. Can lose. Such excessive etching may be performed deliberately, taking into account the unevenness of the thickness of the SIOF film 12 and the instability of the etch depth along the substrate plane.

Referring to FIG. 4C, another stop mask is formed on the SIOF film by a typical ore plate technique. The first silicon oxide film 11 is anisotropically etched so that a contact flow 14 (only one is shown in the figure) is formed through the blocking mask and the wiring channel 13 of the SIOF film 12. The anisotropic etching is performed under typical silicon oxide film etching conditions.

Referring to FIG. 4D, the second silicon oxide film 15 is deposited by plasma CVD to a thickness of 50 nm to cover the entire exposed surface including the inner surface of the wiring channel 13 and the contact holes 14. . Thereafter, the second oxide film 15 and the wiring channel 13 and the portion covering the sidewalls of the contact hole 14 are etched again, and then the tin film 16 as the barrier metal is the SIOF film 12. And by CVD or sputtering to a thickness of 50 nm to cover the sidewalls of the wiring channel 13 and the contact hole 14. The second silicon oxide film 15 and tin film 16 act to avoid a reaction between the fluorine present in the SIOF bar 12 and the metal line (or wiring conductor) to be briefly described.

Referring to FIG. 4E, an aluminum film 17 used as a metal line (or wiring conductor) is deposited by CVD over the entire wafer surface including the contact dispersion 14 and the inside of the wiring channel 13.

Referring to FIG. 4F, the aluminum film 17 is removed by chemical-mechanical polishing except for portions filled in the wiring channel 13 and the contact hole 14. Thus, a metal line (or wiring conductor) shown at 17 'is formed.

As described above, according to the first embodiment of the present invention, the entire first silicon oxide film 11 under the wiring layer acts as an etch stopper film when forming the wiring channel 13 by etching. As described in accordance with the first method, the etch stopper film can be avoided from penetrating during etching. This ensures increased etch margins that facilitate the channel formation process. Moreover, since the low dielectric constant SIOF film 12 is present between adjacent metal Raan or wiring conductors, the eddy current accompanying metal lines (or wiring conductors) can be reduced by about 10%.

Next, referring to Figs. 5A to 5F, a semiconductor device manufacturing method according to the second embodiment of the present invention will be described.

Referring first to FIG. 5A, the semiconductor substrate 20 has a source and drain region 201, a gate electrode 202, and a field silicon oxide film 203 as in the first embodiment. The first silicon oxide film 21 is laminated on the semiconductor substrate 20 to a thickness of 0.6 mu m. Then, the first silicon oxide film 21 is polished chemically and mechanically so as to be flat. Here, the first silicon oxide film 21 is adjusted to 0.5 占 퐉 from the field silicon oxide film 203. On the planarized first silicon oxide film 21, a hydrogen containing amorphous carbon film 22 and a fluorine containing amorphous carbon film 23 are successively laminated to a thickness of 10 nm and 0.5 mu m, respectively. Lamination of each film is performed by plasma CVD. The hydrogen-containing amorphous carbon film 22 serves as a buffer film to increase the adhesion between the first silicon oxide film and the fluorine-containing amorphous carbon film 23.

For example, the stacking of the hydrogen containing amorphous carbon film 22 and the fluorine containing amorphous carbon film 23 is performed in a reaction chamber maintained at a pressure of 2 mT and operated at a RF power of 2 kW. CH ₄ and C ₂ F are supplied as a batch gas to the reaction chamber at a flow ratio of 50 sccm. Therefore, the hydrogen-containing amorphous carbon film 23 and the fluorine-containing amorphous carbon film are successively laminated. As a result, the fluorine-containing amorphous carbon film 23 has a relative dielectric constant of 2.5.

5B and 5C, the wiring channel 24 and the contact hole 25 are formed in a similar manner to that described in the first embodiment. When the wiring channel 24 is formed, etching is performed under the conditions described in the first embodiment. In particular, the reaction chamber is operated at 25 W of RF power maintained at a pressure of 300 mT, and the etching gases of Ar, Cl ₂ and O ₂ are supplied at flow rates of 200 sccm, 150 sccm and 150 sccm, respectively. Under the conditions described above, the fluorine-containing amorphous carbon film 23 has an etch ratio of approximately five times that of the silicon oxide film 21. Therefore, even if excessive etching is performed before the selected etch depth is calculated from the desired thickness of the fluorine-containing amorphous carbon film 23, the entire first silicon oxide film 11 acts as an etch stopper film so that the wiring channel having a uniform thickness ( 13) can be obtained. However, excessive etching may be performed deliberately, taking into account the variation in thickness of the fluorine-containing amorphous carbon film 23 and the instability of the etch depth along the substrate plane.

5D to 5F, the sidewalls of the wiring channel 24 and the contact hole 25 are coated with the second silicon oxide film 26 in a similar manner to the first embodiment. Thereafter, the tin film 27 is disposed as the barrier metal. Next, an aluminum film 28 used as a metal line (or wiring conductor) is disposed by CVD on the entire wafer surface including the contact hole 25 and the inside of the wiring channel 24. The aluminum film 28 is removed by chemical-mechanical polishing except for portions filled in the wiring channel 24 and the contact hole 25. Thus, a metal line (or wiring conductor) shown at 28 'is formed.

As described above, according to the second embodiment of the present invention, the entire first silicon oxide film 21 under the wiring layer acts as an etch stopper film when forming the wiring channel 24 by etching. Therefore, as described in conformity with the conventional first method, the etch stopper film can be avoided from penetrating during etching. This ensures increased etch margins that facilitate the channel formation process. Moreover, since the low dielectric constant fluorine-containing amorphous carbon film 23 is present between adjacent metal lines or wiring conductors, the vortex capacity accompanying the metal lines can be reduced by about 30%.

As described above, in the semiconductor device of the present invention and the method of manufacturing the same, the SIOF film or organic insulator film having a high dielectric constant and a high etch ratio is interposed between the metal lines (or wiring conductors) of the wiring layer. Therefore, the silicon oxide film under the wiring layer acts as an etch stopper film. Compared with the conventional first method in which the etch stopper film is additionally provided, the metal line (or wiring conductor) forming process is simplified. Moreover, the etch stopper film used in the first conventional method is a high dielectric film such as a silicon nitride film. In contrast, in the present invention, a low dielectric insulator film is present between adjacent metal lines or wiring conductors. Therefore, the eddy current capacity associated with the metal line (or wiring conductor) is reduced by about 10 to 30%.

While the foregoing has been described in accordance with some preferred embodiments, various other methods will be readily apparent to those skilled in the art. For example, lamination may be performed by using various other known techniques. In addition, the etching conditions may differ from those described above. Although a single wiring layer on a semiconductor device is described, the present invention can be applied to the formation of second and subsequent wiring layers of multiple stacked metal constructions.

Claims (6)

A semiconductor layer, and a first insulating film formed on the semiconductor layer; First and second wiring conductors formed on the first insulator film having a space left between them; And a second insulator film formed on the first insulator film having a second insulator film buried in the space; And the second insulator film has a higher etch ratio than the first insulator film and a relative dielectric constant lower than that of the first insulator film. The semiconductor device according to claim 1, wherein the first insulator film is a silicon oxide film, and the second insulator film is a silicon oxide film to which fluorine is added. The semiconductor device according to claim 1, wherein said first insulator film is a silicon oxide film and said second insulator film is fluorine-containing amorphous carbon. A semiconductor device manufacturing method comprising a semiconductor layer, comprising: forming a first insulator film on the semiconductor layer; Forming a second insulator film on the first insulator film, the second insulator film having an etch ratio higher than that of the first insulating film and a relative dielectric constant lower than that of the first insulator film; Selectively nicking the first and second set portions of the second insulator film by using the first insulator film as an etch stopper to form first and second wiring channels; And selectively forming first and second wiring conductors in the first and second wiring channels. The method of claim 4, wherein the first insulator film is a silicon oxide film, and the second insulator film is a silicon oxide film to which fluorine is added. 5. The method of claim 4, wherein the first insulator film is a silicon oxide film and the second insulator film is fluorine-containing amorphous carbon. ※ Note: The disclosure is based on the initial application.