KR980006404A - Static RAM cell manufacturing method - Google Patents

Static RAM cell manufacturing method Download PDF

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Publication number
KR980006404A
KR980006404A KR1019960025396A KR19960025396A KR980006404A KR 980006404 A KR980006404 A KR 980006404A KR 1019960025396 A KR1019960025396 A KR 1019960025396A KR 19960025396 A KR19960025396 A KR 19960025396A KR 980006404 A KR980006404 A KR 980006404A
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South Korea
Prior art keywords
forming
conductive film
film
oxide film
manufacturing
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KR1019960025396A
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Korean (ko)
Inventor
손광식
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960025396A priority Critical patent/KR980006404A/en
Publication of KR980006404A publication Critical patent/KR980006404A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 TFT를 노드소자로 구비한 에스램 제조방법에 있어서, 반도체 기판 상에 층간 절연막과 1차 산화막이 도포된 단계; 기판 상의 1차 산화막을 선택 식각하는 단계; 선택식각한 소정의 활성영역에 게이트 형성을 위한 1차 전도막을 증착하고 게이트 전극을 형성하는 단계; 게이트 전극상에 2차산화막을 도포하고 데이터 저장 노드부위를 노출시키는 단계; 2차 산화막상에 채널을 형성하기위한 2차 전도막을 형성하는 단계; 상기 기판상의 활성영역에 1차전도막과 2차전도막이 오버랩된 영역을 부분 식각하는 단계; 감광막 패턴을 사용한 상기 콘택부위에 플러그를 형성하는 단계; 표면의 평탄화를 위한 배선층간 절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 에스램 제조방법에 관한 것으로 노드소자인 TFT를 구성하는 경우 PN 접합다이오드 형성에 대해 소자간 배선 재료로서 안정성과 전도성이 높은 텅스텐을 증착하는 공정으로서, PN 접합 다이오드 형성에 의한 소자를 구동하는 정전압이 불규칙하게 인가되어 셀데이타 보존능력을 방해하여 소자간 신뢰성을 제한하는 종래의 에스램을 제조방법을 개선한 효과가 있다.The present invention provides a method of manufacturing an esr ram having a TFT as a node device, comprising: a step of applying an interlayer insulating film and a first oxide film on a semiconductor substrate; Selectively etching the first oxide film on the substrate; Depositing a first conductive film for gate formation in a selectively etched active region and forming a gate electrode; Applying a secondary oxide film on the gate electrode and exposing a data storage node region; Forming a secondary conductive film for forming a channel on the secondary oxide film; Partially etching a region where the primary conductive film and the secondary conductive film overlap the active region on the substrate; Forming a plug on the contact portion using a photoresist pattern; And forming a wiring interlayer insulating film for planarization of the surface. The method of manufacturing an ESRAM according to the present invention is characterized in that, when forming a TFT that is a node device, stability and conductivity As a process for depositing high tungsten, there is an effect of improving the manufacturing method of the conventional ESRAM in which the constant voltage for driving the device by the formation of the PN junction diode is irregularly applied, thereby hindering the cell data storage capability and restricting the reliability between the devices .

Description

스태틱램 셀 제조방법Static RAM cell manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 제1도의 스태틱램 셀 하이노드영역의 A-A′ 단면도.FIG. 2 is a cross-sectional view taken along line A-A 'of the static RAM cell high node region of FIG. 1;

Claims (6)

TFT를 노드소자로 구비한 에스램 제조방법에 있어서, 반도체 기판 상에 층간 절연막과 1차 산화막이 형성한 단계; 기판 상의 1차산화막을 선택 식각하는 단계; 선택 식각한 소정의 활성영역에 게이트 형성을 위한 1차전도막을 형성하고 게이트 전극을 형성하는 단계; 게이트 전극상에 2차 산화막을 도포하고 데이터 저장 노드부위를 노출시키는 단계; 2차 산화막상에 채널을 형성하기 위한 2차 전도막을 형성하는 단계; 상기 기판상의 활성영역에 1차 전도막과 2차 전도막이 오버랩된 영역을 부분식각하는 단계; 감광막 패턴을 사용한 상기 콘택부위에 플러그를 형성하는 단계; 표면의 평탄화를 위한 배선층간 절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한 에스램 제조방법.1. A method of manufacturing an esr ram having a TFT as a node element, the method comprising: forming an interlayer insulating film and a first oxide film on a semiconductor substrate; Selectively etching the first oxide film on the substrate; Forming a first conductive film for forming a gate in a predetermined active region selectively etched and forming a gate electrode; Applying a secondary oxide film on the gate electrode and exposing a data storage node region; Forming a secondary conductive film for forming a channel on the secondary oxide film; Partially etching a region where the primary conductive film and the secondary conductive film overlap the active region on the substrate; Forming a plug on the contact portion using a photoresist pattern; And forming a wiring interlayer insulating film for planarization of the surface. 제1항에 있어서, 1차 전도막과 2차 전도막이 오버랩된 콘택홀 부위에 소자간 배선재료로서 텅스텐을 선택적으로 증착하는 것을 특징으로 하는 에스램 제조방법.The method of manufacturing an esam according to claim 1, wherein tungsten is selectively deposited as an inter-element wiring material in a contact hole portion where the primary conductive film and the secondary conductive film overlap. 제2항에 있어서, 상기 배선재료로 텅스텐을 오버랩된 콘택홀 부위에 증착할 시 2차 전도막과 1차전도막의 일부까지 식각되는 것을 특징으로 하는 에스램 제조방법.3. The method of claim 2, wherein the tungsten is etched to a portion of the first conductive film and the second conductive film when the wiring material is deposited on the overlapped contact hole. 제1항에 있어서, 선택 식각한 소정의 활성영역에 게이트 형성을 위한 1차전도막은 P+ 폴리실리콘 증착하는 것을 특징으로 하는 에스램 제조방법.2. The method of claim 1, wherein the primary electroless film for gate formation in the selectively etched active region is P + polysilicon deposited. 제1항에 있어서, 2차 산화막상에 채널을 형성하기 위한 2차 전도막은 N+ 폴리실리콘을 증착하는 것을 특징으로 하는 에스램 제조방법.The method of claim 1, wherein the secondary conductive film for forming a channel on the secondary oxide film deposits N + polysilicon. 제1항에 있어서, 표면의 평탄화를 위한 배선층간 절연막은 BPSG막을 증착하는 것을 특징으로한 에스램 제조방법.The method according to claim 1, wherein the wiring interlayer insulating film for surface planarization is formed by depositing a BPSG film.
KR1019960025396A 1996-06-28 1996-06-28 Static RAM cell manufacturing method KR980006404A (en)

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