KR980006359A - How to form a CMOS transistor - Google Patents

How to form a CMOS transistor Download PDF

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Publication number
KR980006359A
KR980006359A KR1019960024520A KR19960024520A KR980006359A KR 980006359 A KR980006359 A KR 980006359A KR 1019960024520 A KR1019960024520 A KR 1019960024520A KR 19960024520 A KR19960024520 A KR 19960024520A KR 980006359 A KR980006359 A KR 980006359A
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well
amorphous silicon
forming
silicon film
oxide film
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KR1019960024520A
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Korean (ko)
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KR100224586B1 (en
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황준
김천수
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 소자 특성이 개선된 씨모스 트랜지스터 형성방법이 개시된다. 개시된 본 발명은, N웰 및 P웰램이 구비된 반도체 기판을 제공하는 단계; N웰 및 P웰이 접하는 부분에 필드 산화막을 형성하는 단계; 결과물 표면에 게이트 산화막을 형성하는 단계; 게이트 산화막 상부에 비정질 실리콘막을 증착하는 단계; N웰 영역 상부의 비정질 실리콘막에 P형의불순물을 주입하는 단계; 및 P웰 영역 상부의 비정질 실리콘막에 N형의 불순물을 주입하는 단계를 포함하는 것을 특징으로 한다. 본 발명에 의하면, 게이트 전극 물질로서, 비균일한 결정립계를갖는 비정질 실리콘막을 형성하여, 선택적으로 불순물을 확산을 방지하므로써, 씨 모스 게이트의 전도 특성이 개선되고, 문턱 전압이 변화되지 않으므로 소자의 신뢰성이 증대된다.A method of forming a CMOS transistor with improved device characteristics is disclosed. The disclosed invention provides a method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate provided with an N well and a P well; Forming a field oxide film on a portion where the N well and the P well are in contact with each other; Forming a gate oxide film on the surface of the resultant product; Depositing an amorphous silicon film over the gate oxide film; Implanting a P-type impurity into the amorphous silicon film above the N well region; And implanting an N-type impurity into the amorphous silicon film above the P-well region. According to the present invention, by forming an amorphous silicon film having a non-uniform crystal grain system as a gate electrode material and selectively preventing the diffusion of impurities, the conduction characteristics of the CMOS gate are improved and the threshold voltage is not changed, Is increased.

Description

씨모스 트랜지스터 형성방법How to form a CMOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3a 내지 3c는 본 발명의 씨모스 트랜지스터 형성방법을 설명하기 위한 각 공정 순서별 단면도.FIGS. 3A to 3C are cross-sectional views for explaining a method of forming a CMOS transistor according to each process sequence of the present invention;

Claims (5)

N웰 및 P웰이 구비된 반도체 기판을 제공하는 단계; 상기 N웰 및 P웰이 접하는 부분에 필드 산화막을 형성하는 단계; 결과물 표면에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상부에 비정질 실리콘막을 증착하는 단계; 상기 N웰 영역 상부의 비정질 실리콘막에 P형의 불순물을 주입하는 단계; 및 상기 P웰 영역 상부의 비정질 실리콘막에 N형의 불순물을 주입하는 단계를 포함하는 것을 특징으로 하는 씨모스 트랜지스터 형성방법.Providing a semiconductor substrate having an N well and a P well; Forming a field oxide film on a portion where the N well and the P well are in contact with each other; Forming a gate oxide film on the surface of the resultant product; Depositing an amorphous silicon film on the gate oxide film; Implanting a P-type impurity into the amorphous silicon film above the N-well region; And implanting an N-type impurity into the amorphous silicon film above the P-well region. 제1항에 있어서, 상기 게이트 산화막을 형성하는 단게와, 비정질 실리콘막을 형성하는 단계 사이에 폴리 실리콘막을 증착하는 단계를 부가적으로 포함하는 것을 특징으로 하는 씨모스 트랜지스터 형성방법.2. The method of claim 1, further comprising depositing a polysilicon film between the step of forming the gate oxide film and the step of forming the amorphous silicon film. 제2항에 있어서, 상기 폴리실리콘막의 두께는 100 내지 500A인 것을 특징으로 하는 씨모스 트랜지스터 형성방법.3. The method according to claim 2, wherein the thickness of the polysilicon film is 100 to 500A. 제 1항에 있어서, 상기 N형 및 P형의 불순물이 주입된 비정질 실리콘막에 상부에 금속 실리사이드막을 형성하는 단게를 추가하는 것을 특징으로 하는 씨모스 트랜지스터 형성방법.The method according to claim 1, wherein a step of forming a metal silicide film on the amorphous silicon film into which the N-type and P-type impurities are implanted is added. 제1항 또는 제2항에 있어서, 상기 비정질 실리콘막의 두께는 1000내의 1900A인 것을 특징으로 하는 씨모스 트랜지스터 형성방법.3. The method according to claim 1 or 2, wherein the thickness of the amorphous silicon film is 1900A in 1000.
KR1019960024520A 1996-06-27 1996-06-27 Manufacturing method of cmos transistor KR100224586B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315450B1 (en) * 1999-04-13 2001-11-28 황인길 Method for forming gate electrode of semiconductor devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476036B1 (en) * 1998-07-03 2005-09-26 매그나칩 반도체 유한회사 Semiconductor device and manufacturing method thereof.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315450B1 (en) * 1999-04-13 2001-11-28 황인길 Method for forming gate electrode of semiconductor devices

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