KR980006310A - Capacitors in DRAM cells and methods of manufacturing the same - Google Patents

Capacitors in DRAM cells and methods of manufacturing the same Download PDF

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KR980006310A
KR980006310A KR1019960021592A KR19960021592A KR980006310A KR 980006310 A KR980006310 A KR 980006310A KR 1019960021592 A KR1019960021592 A KR 1019960021592A KR 19960021592 A KR19960021592 A KR 19960021592A KR 980006310 A KR980006310 A KR 980006310A
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layer
teos
oxide
storage electrode
bumpy
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KR1019960021592A
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KR100249917B1 (en
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쿠앙-차오 첸
투바이 투
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후 홍 치우
모젤 비텔릭 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains

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  • Semiconductor Memories (AREA)

Abstract

본 발명은 DRAM 셀의 적층형 커패시터, 특히 차지하는 면적을 늘리거나 제조 방법을 복잡하게 하지 않고 메모리 캐패시터의 저장 전극 면적을 현저히 증가시키는 DRAM셀의 적층형 커패시터에 관한 것이다. 메모리 커패시터의 저장 전극을 특별히 만들어진 울퉁불퉁한 적층 산화층에 증착하여, 메모리 커패시터의 저장 전극면적이 현저히 증가되어 더 높은 커패시턴스를 제공한다. 그 뒤, 저장 전극의 울퉁불퉁한 표면을 노출시키기 위하여 울퉁불퉁한 적층형 산화층을 제거하고, 저장 전극의 유전체막이 있는 저장 전극의 전체 울퉁불퉁한 표면을 덮은 후 메모리 커패시턴스의 커패시턴스가 추가적으로 증가된다.The present invention relates to a stacked capacitor of a DRAM cell, in particular a stacked capacitor of a DRAM cell that significantly increases the storage electrode area of the memory capacitor without increasing the area occupied or complicated manufacturing method. By depositing the storage electrode of the memory capacitor on a specially made rugged stacked oxide layer, the storage electrode area of the memory capacitor is significantly increased to provide higher capacitance. Thereafter, the uneven stacked oxide layer is removed to expose the uneven surface of the storage electrode, and the capacitance of the memory capacitance is further increased after covering the entire uneven surface of the storage electrode with the dielectric film of the storage electrode.

Description

DRAM 셀의 커패시터 및 그의 제조 방법Capacitors in DRAM cells and methods of manufacturing the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 울퉁불퉁한 적층형 산화층과 그 위의 폴리실리콘층의 주사 전자 현미경 사진4 is a scanning electron micrograph of a bumpy stacked oxide layer and a polysilicon layer thereon according to the present invention.

Claims (12)

a) 실리콘 기판의 표면 내에 게이트 전극(즉, 워드 라인)과, 소오스/드레인 영역과, 그사이에 삽입된 절연막을 포함하는 전계 효과트랜지스터와, 고립된 전계 산화물의 영역을 형성하는 단계와; b) PSG층을 증착하고 그후 PE TEOS의 하부층과 O3/TEOS의 상부층으로 구성된 울퉁불퉁한 적층형 산화층을 증착하는 단계와; c) 울퉁불퉁한 적층현 산화층과 PSG층을 에칭하여 저장 전극 콘택트홀을 형성하는 단계와, d) 어니일링하고 그후 폴리실리콘층을 증착하는 단계와; e) 폴리실리콘층상에 유전체층을 형성한 후 전계 효과 트랜지스터의 소오스 와 드레인 영역 중의 하나에 연결된 저장 전극을 형성하기 위하여 패터닝하는 단계; f) 폴리실리콘층을 증착하여 플레이트 전극을 형성하고 패터닝하는 단계와; g) 절연층을 증착한 뒤 비트라인 톤택트홀을 형성하기 위하여 패터닝하는 단계와; h) 전계 효과 트랜지스터의 소오스 또는 드레인 영역 중의 하나에 연결된 비트 라인을 폴리실리콘층의 증착과 그후의 패터넝에 의하여 형성하는 단계를 포함하는 DRAM 셀의 적층형 메모리 커패시터를 제조하는 방법.a) forming a field effect transistor comprising a gate electrode (ie, a word line), a source / drain region, and an insulating film interposed therebetween in the surface of the silicon substrate, and an isolated field oxide region; b) depositing a PSG layer and then depositing a bumpy stacked oxide layer consisting of a bottom layer of PE TEOS and a top layer of O 3 / TEOS; c) etching the rugged laminated string oxide layer and the PSG layer to form storage electrode contact holes, d) annealing and then depositing a polysilicon layer; e) forming a dielectric layer on the polysilicon layer and patterning to form a storage electrode connected to one of the source and drain regions of the field effect transistor; f) depositing a polysilicon layer to form and pattern a plate electrode; g) depositing an insulating layer and patterning to form a bitline tone tact hole; h) forming a bit line connected to one of the source or drain regions of the field effect transistor by deposition of a polysilicon layer and subsequent patterning. 제1항에 있어서, 상기 절연층은 산화물인 것을 특징으로 하는 방법.The method of claim 1 wherein the insulating layer is an oxide. 제1항에 있어서, 상기 울퉁불퉁한 적층형 산화층은 하부의 열산화층과 상부의 O3/TEOS층을 포함하는 것을 특징으로 하는 방법.The method of claim 1, wherein the bumpy stacked oxide layer comprises a lower thermal oxide layer and an upper O 3 / TEOS layer. 제1항에 있어서, 상기 울퉁불퉁한 적층형 산화층이 TEOS법에 의하여 구성된 PSG의 하부층과 O3/TEOS의 상부층을 포함하는 것을 특징으로 하는 방법.The method of claim 1, wherein the bumpy stacked oxide layer comprises a lower layer of PSG and an upper layer of O3 / TEOS constructed by the TEOS method. 제1항에 있어서, 상기 울퉁불퉁한 적층형 산화층이 LPCVD 또는 PECVD에 으하여 형성되는 하바의 질화층과 O3/TEOS의 상부층을 포함하는 것을 특징으로 하는 방법.2. The method of claim 1, wherein the rugged stacked oxide layer comprises a top layer of O 3 / TEOS and a haba nitride layer formed by LPCVD or PECVD. 제1항에 있어서, 상기 유전체막은 CVD에 의하여 형성되는 ONO(Oxide-Nitride-Oxide)인 것을 특징으로 하는 방법.The method of claim 1, wherein the dielectric film is Oxide-Nitride-Oxide (ONO) formed by CVD. 제1항에 있어서, 상기 유전체막은 도핑된 폴리실리콘층의 열산화에 의하여 형성되는 것을 특징으로 하는 방법.The method of claim 1, wherein the dielectric film is formed by thermal oxidation of a doped polysilicon layer. 실리콘기판과; 게이트 전극, 드레인/소오스 영역 및 그 사이의 절연막을 포함하는 전계 효과트랜지스터; 전계 산화물의 고립된 영역; 게이트 전극 상에 놓인 PSG층; PE TEOS의 상부층과 O3/TEOS의 상부층으로 구성된 저장 전극 밑의 울퉁불퉁한 적층형 산화층; 전계 효과트랜지스터의 소오스와 드레인 영역 중의 하나에 연결된 폴리실리콘층으로 만들어진 저장 전극; 저장 전극을 덮는 유전체막; 도핑된 폴리실리콘층으로 만들어진 플레이트 전극; 플레이트전극 위에 놓인 절연층; 전계 효과 트랜지스터의 소오스와 드레인 영역중의 하나에 연결된 폴리실리콘층으로 마드러진 비트 라인을 포함하는 DRAM 셀의 메모리 커패시터.A silicon substrate; A field effect transistor comprising a gate electrode, a drain / source region, and an insulating film therebetween; An isolated region of the field oxide; A PSG layer overlying the gate electrode; A bumpy stacked oxide layer under the storage electrode consisting of a top layer of PE TEOS and a top layer of O 3 / TEOS; A storage electrode made of a polysilicon layer connected to one of the source and drain regions of the field effect transistor; A dielectric film covering the storage electrode; A plate electrode made of a doped polysilicon layer; An insulating layer on the plate electrode; A memory capacitor in a DRAM cell comprising a bit line made of a polysilicon layer connected to one of the source and drain regions of the field effect transistor. 제8항에 있어서, 상기 절연층이 산화물인 것을 특징으로 하는 DRAM 셀의 메모리 커패시터.The memory capacitor of claim 8, wherein the insulating layer is an oxide. 제8항에 있어서,상기 울퉁불퉁한 적층형 산화층이 하부의 열산화층과 상부의 O3/TEOS층을 포함하는 것을 특징으로 하는 DRAM 셀의 메모리 커패시터.The memory capacitor of claim 8, wherein the bumpy stacked oxide layer comprises a lower thermal oxide layer and an upper O 3 / TEOS layer. 제8항에 잇어서, 상기 울퉁불퉁한 적층형 산화층이 LPCVD 또는 PECVD로 형성된 하부의 질화층과 O3/TEOS의 상부층을 포함하는 것을 특징으로 하는 DRAM 셀의 메모리 커패시터.9. The memory capacitor of claim 8 wherein the bumpy stacked oxide layer comprises a lower nitride layer formed by LPCVD or PECVD and an upper layer of O3 / TEOS. 제8항에 있어서, 상기 울퉁불퉁한 적층형 산화층이 LPCVD 또는 PECVD로 형성된 하부의 질화층과 O3/TEOS의 상부틍을 포함하는 것을 특징으로 하는 DRAM 셀의 메모리 커패시터.9. The memory capacitor of claim 8 wherein the bumpy stacked oxide layer comprises a lower nitride layer formed by LPCVD or PECVD and a top 틍 of O3 / TEOS.
KR1019960021592A 1996-06-14 1996-06-14 Manufacturing method of capacitor in dram cell KR100249917B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511397B1 (en) * 1998-08-06 2005-11-24 삼성전자주식회사 Method for forming connect hole of semiconductor device

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KR100879744B1 (en) 2002-12-30 2009-01-21 주식회사 하이닉스반도체 Capacitor Manufacturing Method of Semiconductor Device

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JP2633395B2 (en) * 1990-12-12 1997-07-23 シャープ株式会社 Method for manufacturing semiconductor memory device
JPH0567732A (en) * 1991-09-05 1993-03-19 Oki Electric Ind Co Ltd Semiconductor element manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511397B1 (en) * 1998-08-06 2005-11-24 삼성전자주식회사 Method for forming connect hole of semiconductor device

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