KR980006306A - Capacitor Formation Method in Semiconductor Device - Google Patents

Capacitor Formation Method in Semiconductor Device Download PDF

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Publication number
KR980006306A
KR980006306A KR1019960020372A KR19960020372A KR980006306A KR 980006306 A KR980006306 A KR 980006306A KR 1019960020372 A KR1019960020372 A KR 1019960020372A KR 19960020372 A KR19960020372 A KR 19960020372A KR 980006306 A KR980006306 A KR 980006306A
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South Korea
Prior art keywords
forming
hsg polysilicon
amorphous silicon
temperature
film pattern
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KR1019960020372A
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Korean (ko)
Inventor
유차영
김영선
심세진
박영옥
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김광호
삼성전자 주식회사
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Priority to KR1019960020372A priority Critical patent/KR980006306A/en
Publication of KR980006306A publication Critical patent/KR980006306A/en

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  • Semiconductor Integrated Circuits (AREA)

Abstract

반도체 장치의 커패시터 형성방법이 개시되어 있다. 이 발명은 반도체기판 상에 비정질 실리콘막 패턴을 형성하는 단계와, 상기 비정질 실리콘막 패턴 표면에 HSG 폴리실리콘막을 형성하는 단계와, 상기 HSG폴리실리콘막 상에 유전막 및 플레이트 전극을 차례로 형성하는 단계를 구비하는 반도체장치의 커패시터 형성방법에 있어서, 상기 HSG 폴리실리콘막을 형성하는 단계는 상기 비정질 실리콘막 패턴이 형성된 결과물을 제1 온도에서 실리콘 소스 가스를 사용하여 상기 비정질 실리콘막 패턴표면에 HSG폴리실리콘 핵을 형성하고, 상기 HSG 폴리실리콘 핵이 형성된 결과물을 상기 제1 온도보다 높은 제2온도에서 어닐링함으로써 상기 비정질 실리콘막 패턴 표면에 HSG 폴리실리콘막을 형성하는 것을 특징으로 한다. 이에 따라, 비정질 실리콘막 패턴 표면에 볼드 디펙트가 발생하는 것을 억제시키면서 균일한 HSG폴리실리콘막을 형성할 수 있으므로 비정질 실리콘막 패턴 및 HSG 폴리실리콘막으로 구성되는 축적전극의 표면적을 극대화시킬 수 있다.A method of forming a capacitor of a semiconductor device is disclosed. The present invention includes forming an amorphous silicon film pattern on a semiconductor substrate, forming an HSG polysilicon film on the surface of the amorphous silicon film pattern, and sequentially forming a dielectric film and a plate electrode on the HSG polysilicon film. In the method of forming a capacitor of a semiconductor device, the forming of the HSG polysilicon film may include forming an HSG polysilicon nucleus on the surface of the amorphous silicon film pattern using a silicon source gas at a first temperature. And forming an HSG polysilicon film on the surface of the amorphous silicon film pattern by annealing the resultant product having the HSG polysilicon nucleus formed at a second temperature higher than the first temperature. As a result, a uniform HSG polysilicon film can be formed while suppressing the occurrence of bold defects on the surface of the amorphous silicon film pattern, thereby maximizing the surface area of the storage electrode composed of the amorphous silicon film pattern and the HSG polysilicon film.

Description

반도체 장치의 커패시터 형성방법Capacitor Formation Method in Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 4도는 및 제 5도는 본 발명에 의한 커패시터 형성방법을 설명하기 위한 단면도들.4 and 5 are cross-sectional views illustrating a method of forming a capacitor according to the present invention.

Claims (6)

반도체기판 상에 비정질 실리콘막 패턴을 형성하는 단계와, 상기 비정질 실리콘막 패턴 표면에 HSG 폴리실리콘막을 형성하는 단계와, 상기 HSG폴리실리콘막 상에 유전막 및 플레이트 전극을 차례로 형성하는 단계를 구비하는 반도체장치의 커패시터 형성방법에 있어서, 상기 HSG 폴리실리콘막을 형성하는 단계는 상기 비정질 실리콘막 패턴이 형성된 결과물을 제1온도에서 실리콘 소스 가스를 사용하여 상기 비정질 실리콘막 패턴 표면에 HSG 폴리실리콘 핵을 형성하고, 상기 HSG 폴리실리콘 핵이 형성된 결과물을 상기 제1 온도보다 높은 제2온도에서 어닐링함으로써 상기 비정질 실리콘막 패턴표면에 HSG폴리실리콘막을 형성하는 것을 특징으로 하는 반도체장치의 커패시터 형성방법.Forming an amorphous silicon film pattern on the semiconductor substrate, forming an HSG polysilicon film on the surface of the amorphous silicon film pattern, and sequentially forming a dielectric film and a plate electrode on the HSG polysilicon film. In the method of forming a capacitor of the device, the forming of the HSG polysilicon film comprises forming an HSG polysilicon nucleus on the surface of the amorphous silicon film pattern by using a silicon source gas at a first temperature on the resultant product of the amorphous silicon film pattern. And forming an HSG polysilicon film on the amorphous silicon film pattern surface by annealing the resultant product on which the HSG polysilicon nucleus is formed at a second temperature higher than the first temperature. 제1항에 있어서, 상기 제1온도 및 상기 제2온도는 각각 580℃내지 595℃ 및 605℃내지 620℃인 것을 특징으로 하는 반도체장치의 커패시터 형성방법.The method of claim 1, wherein the first temperature and the second temperature are 580 ° C. to 595 ° C. and 605 ° C. to 620 ° C., respectively. 제1항에 있어서, 상기 실리콘 소스 가스는 사일레인()가스 또는 다이사일레인() 가스인 것을 특징으로 하는 반도체장치의 커패시터 형성방법.The method of claim 1, wherein the silicon source gas is silane ( ) Gas or Die Silane A method of forming a capacitor of a semiconductor device, characterized in that the gas. 반도체기판 상에 비정질 실리콘막 패턴을 형성하는 단계와, 상기비정질 실리콘막 패턴 표면에 HSG 폴리실리콘막을 형성하는 단계와, 상기 HSG 폴리실리콘막 상에 유전막 및 플레이드 전극을 차례로 형성하는 단계를 구비하는 반도체장치의 커패시터 형성방법에 있어서, 상기 HSG 폴리실리콘막을 형성하는 단계는 상기 비정질 실리콘 막 패턴이 형성된 결과물을 제1온도에서 실리콘 소스 가스를 사용하여 상기 비정질 실리콘막 패턴표면에 HSG폴리실리콘핵을 형성하고, 상기 HSG 폴리실리콘 핵이 형성된 결과물을 상기 제1온도보다 낮은 제2 온도에서 어닐링함으로써 상기 비정질 실리콘막 패턴표면에 HSG폴리실리콘막을 형성하는 것을 특징으로 하는 반도체장치의 커패시터 형성방법.Forming an amorphous silicon film pattern on the semiconductor substrate, forming an HSG polysilicon film on the surface of the amorphous silicon film pattern, and sequentially forming a dielectric film and a plated electrode on the HSG polysilicon film. In the method of forming a capacitor of a semiconductor device, the forming of the HSG polysilicon film may include forming an HSG polysilicon core on the surface of the amorphous silicon film pattern using a silicon source gas at a first temperature. And annealing the resultant product on which the HSG polysilicon nucleus is formed at a second temperature lower than the first temperature to form an HSG polysilicon film on the amorphous silicon film pattern surface. 제4항에 잇어서, 상기 제1온도 및 상기 제2 온도는 각각 605℃내지 610℃ 및 585℃내지 595℃인 것을 특징으로 하는 반도체장치의 커패시터 형성방법.The method of claim 4, wherein the first temperature and the second temperature are 605 ° C. to 610 ° C. and 585 ° C. to 595 ° C., respectively. 제4항에 잇어서, 상기 실리콘 소스 가스는 사일레인()가스 또는 다이사일레인() 가스인 것을 특징으로 하는 반도체장치의 커패시터 형성방법.The method of claim 4, wherein the silicon source gas is silane ( ) Gas or Die Silane A method of forming a capacitor of a semiconductor device, characterized in that the gas.
KR1019960020372A 1996-06-07 1996-06-07 Capacitor Formation Method in Semiconductor Device KR980006306A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100718837B1 (en) * 2004-12-30 2007-05-16 삼성전자주식회사 Method for manufacturing a capacitor having an HSG silicon layer and Method for manufacturing a semiconductor device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100718837B1 (en) * 2004-12-30 2007-05-16 삼성전자주식회사 Method for manufacturing a capacitor having an HSG silicon layer and Method for manufacturing a semiconductor device using the same

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