KR980005980A - Morse transistor test pattern formation method - Google Patents

Morse transistor test pattern formation method Download PDF

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Publication number
KR980005980A
KR980005980A KR1019960026470A KR19960026470A KR980005980A KR 980005980 A KR980005980 A KR 980005980A KR 1019960026470 A KR1019960026470 A KR 1019960026470A KR 19960026470 A KR19960026470 A KR 19960026470A KR 980005980 A KR980005980 A KR 980005980A
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KR
South Korea
Prior art keywords
mos transistor
test pattern
forming
transistor test
film
Prior art date
Application number
KR1019960026470A
Other languages
Korean (ko)
Inventor
김경일
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960026470A priority Critical patent/KR980005980A/en
Publication of KR980005980A publication Critical patent/KR980005980A/en

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  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 반도체 장치의 모스 트랜지스터 동작 특성을 측정하기 위해 스크라이브 라인상에 형성되는 모스 트랜지스터 레스트 패턴 형성방법에 있어서, 상기 스크라이브 라인 상에 게이트 산화막, 게이트 전극, 활성영역이 형성된 모스 트랜지스터 구조 상부에 소정의 절연막을 형성하는 단계 및, 상기 게이트 산화막 및 상기 절연막을 보호하기 위하여 전체구조 상부에 폴리 실리콘막을 형성한 후, 이후 형성될 콘택홀과 오버랩 되지 않도록 선택식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A MOS transistor reset pattern forming method for forming MOS transistor reset pattern on a scribe line for measuring a MOS transistor operating characteristic of a semiconductor device, the MOS transistor reset pattern forming method comprising the steps of: Forming a polysilicon film on the entire structure to protect the gate oxide film and the insulating film, and then selectively etching the polysilicon film so as not to overlap with the contact hole to be formed thereafter .

Description

모스 트랜지스터 테스트 패턴 형성방법Morse transistor test pattern formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 일실시예에 따른 반도체 장치의 모스 트랜지스터 테스트 패턴 단면도.FIG. 2 is a cross-sectional view of a MOS transistor test pattern of a semiconductor device according to an embodiment of the present invention; FIG.

Claims (1)

반도체 장치의 모스 트랜지스터 동작 특성을 측정하기 위해 스크라이브 라인 상에 형성되는 모스 트랜지스터 테스트 패턴 형성방법에 있어서, 상기 스크라이브 라인 상에 게이트 산화막, 게이트 전극, 활성영역이 형성된 모스 트랜지스터 구조 상부에 소정의 절연막을 형성하는 단계 및, 상기 게이트 산화막 및 상기 절연막을 보호하기 위하여 전체구조 상부에 폴리 실리콘막을 형성한 후, 이후 형성될 콘택홀과 오버랩되지 않도록 선택식각하는 단계를 포함하여 이루어진 반도체 장치의 모스 트랜지스터 테스트 패턴 형성방법.A MOS transistor test pattern forming method for forming a MOS transistor test pattern on a scribe line for measuring MOS transistor operating characteristics of a semiconductor device, comprising the steps of: forming a MOS transistor structure in which a gate oxide film, a gate electrode and an active region are formed on the scribe line, And forming a polysilicon film on the entire structure to protect the gate oxide film and the insulating film and then selectively etching the polysilicon film so as not to overlap with the contact holes to be formed thereafter. / RTI > ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960026470A 1996-06-29 1996-06-29 Morse transistor test pattern formation method KR980005980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960026470A KR980005980A (en) 1996-06-29 1996-06-29 Morse transistor test pattern formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960026470A KR980005980A (en) 1996-06-29 1996-06-29 Morse transistor test pattern formation method

Publications (1)

Publication Number Publication Date
KR980005980A true KR980005980A (en) 1998-03-30

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Family Applications (1)

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KR1019960026470A KR980005980A (en) 1996-06-29 1996-06-29 Morse transistor test pattern formation method

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KR (1) KR980005980A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100409032B1 (en) * 2001-11-23 2003-12-11 주식회사 하이닉스반도체 Method of forming a test pattern, method of measuring an etching characteristic using the same and circuit for measurement of the etching characteristic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100409032B1 (en) * 2001-11-23 2003-12-11 주식회사 하이닉스반도체 Method of forming a test pattern, method of measuring an etching characteristic using the same and circuit for measurement of the etching characteristic

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