KR950034841A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR950034841A
KR950034841A KR1019950001980A KR19950001980A KR950034841A KR 950034841 A KR950034841 A KR 950034841A KR 1019950001980 A KR1019950001980 A KR 1019950001980A KR 19950001980 A KR19950001980 A KR 19950001980A KR 950034841 A KR950034841 A KR 950034841A
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KR
South Korea
Prior art keywords
gate electrode
polysilicon
forming
semiconductor device
region
Prior art date
Application number
KR1019950001980A
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Korean (ko)
Inventor
다카시 우메모토
히로시 다카하시
Original Assignee
이토 기요시
세이코덴시고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이토 기요시, 세이코덴시고교 가부시키가이샤 filed Critical 이토 기요시
Publication of KR950034841A publication Critical patent/KR950034841A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 유도력이 높은 하이-브레이크다운-전압 MOS트랜지스터에 관한 것이다. 하이-브레이크다운-전압 MOS 트랜지스터의 게이트 전극은 드레인 영역의 전도 타입과는 다른 전도 타입의 폴리실리콘으로 만들어진다. 고-저항 영역은 적어도 드레인측 단부를 포함하는 게이트 전극의 일부에 형성된다.The present invention relates to a high-breakdown-voltage MOS transistor with high inductive force. The gate electrode of the high-breakdown-voltage MOS transistor is made of polysilicon of a conductivity type different from that of the drain region. The high-resistance region is formed in a portion of the gate electrode that includes at least the drain side end.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예에 따른 하이-브레이크다운-전압 MOS 트랜지스터의 개략적인 단면도이다. 제2도는 본 발명의 제2실시예에 따른 하이-브레이크다운-전압 MOS 트랜지스터의 개략적인 단면도이다, 제3도는 본 발명의 제3실시예에 따른 하이-브레이크다운-전압 MOS 트랜지스터의 개략적인 단면도이다.1 is a schematic cross-sectional view of a high-breakdown-voltage MOS transistor according to a first embodiment of the present invention. 2 is a schematic cross-sectional view of a high-breakdown-voltage MOS transistor according to a second embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a high-breakdown-voltage MOS transistor according to a third embodiment of the present invention. to be.

Claims (4)

드레인 영역과; 적어도 그 드레인측 단부를 포함하는 부분에 고-저항 영역을 가지는 게이트 전극으로 구성된 MOS 트랜지스터 반도체 장치.A drain region; A MOS transistor semiconductor device comprising a gate electrode having a high-resistance region in at least a portion including its drain side end portion. 제1항에 있어서, 상기 게이트 전극 내에 형성된상기 고-저항 영역은 상기 드레인 영역의 전도 타입과는 다른 전도 타입인 것을 특징으로 하는 MOS 트랜지스터 반도체 장치.The MOS transistor semiconductor device of claim 1, wherein the high-resistance region formed in the gate electrode is of a different conductivity type than that of the drain region. 폴리실리콘 게이트 전극을 형성하는 단계와; 폴리실리콘막을 형성함으로써, 상기 폴리실리콘 게이트 전극보다 저항이 큰 측벽을 상기 폴리실리콘 게이트 전극의 외부 플렌지 영역에 형성하는 단계와; 상기 측벽을 불균일하게 에칭하는 단계로 구성된 반도체장치 제조방법.Forming a polysilicon gate electrode; Forming a polysilicon film, thereby forming a sidewall having a greater resistance than the polysilicon gate electrode in an outer flange region of the polysilicon gate electrode; And unevenly etching the sidewalls. 폴리실리콘 게이트 전극을 형성하는 단계와; 그 위에 폴리실리콘 층을 형성하는 단계와; 저-저항 영역을 형성하기 위하여, 상기 저면의 폴리실리콘 게이트 전극에서보다 더 많은 양의 불순물을 유입시킴으로써 상기 폴리실리콘 층의 내부에 불순물을 도핑하는 단계와; 상기 게이트 전극을 형성하기 위해 에칭하는 단계로 구성된 반도체장치 제조방법.Forming a polysilicon gate electrode; Forming a polysilicon layer thereon; Doping the inside of the polysilicon layer by introducing more impurities than at the bottom polysilicon gate electrode to form a low-resistance region; And etching to form the gate electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950001980A 1994-02-02 1995-01-28 Semiconductor device and manufacturing method thereof KR950034841A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6011240A JPH07221291A (en) 1994-02-02 1994-02-02 Semiconductor device and its manufacture
JP94-11240 1994-02-02

Publications (1)

Publication Number Publication Date
KR950034841A true KR950034841A (en) 1995-12-28

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JP (1) JPH07221291A (en)
KR (1) KR950034841A (en)
TW (1) TW283262B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3854290B2 (en) 2004-06-17 2006-12-06 株式会社東芝 Semiconductor device and manufacturing method thereof
JP5280056B2 (en) * 2008-01-10 2013-09-04 シャープ株式会社 MOS field effect transistor
JP5582030B2 (en) * 2010-12-28 2014-09-03 富士通セミコンダクター株式会社 MOS transistor and manufacturing method thereof
JP6318786B2 (en) 2014-04-04 2018-05-09 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

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Publication number Publication date
JPH07221291A (en) 1995-08-18
TW283262B (en) 1996-08-11

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