KR980005827A - Interlayer insulating film of semiconductor device and manufacturing method thereof - Google Patents

Interlayer insulating film of semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR980005827A
KR980005827A KR1019960024510A KR19960024510A KR980005827A KR 980005827 A KR980005827 A KR 980005827A KR 1019960024510 A KR1019960024510 A KR 1019960024510A KR 19960024510 A KR19960024510 A KR 19960024510A KR 980005827 A KR980005827 A KR 980005827A
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KR
South Korea
Prior art keywords
oxide film
film
insulating film
semiconductor device
interlayer insulating
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KR1019960024510A
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Korean (ko)
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안희복
김천수
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김주용
현대전자산업 주식회사
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Priority to KR1019960024510A priority Critical patent/KR980005827A/en
Publication of KR980005827A publication Critical patent/KR980005827A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 개선된 층간 절연막 및 그 제조방법이 개시된다. 본 발명의 층간 절연막은 반도체 소자의 층간 평탄화 막으로, 수분 함량이 적고, 유전율 및 매립 특성이 우수한 플로우르화 실리콘 산화막이 이용되어, 수분 확산이 배제되어, 금속막의 부식이 방지되고, 소자의 특성 및 동작 속도가 개선된다.An improved interlayer insulating film and a method of manufacturing the same are disclosed. The interlayer insulating film of the present invention is an interlayer planarizing film of a semiconductor device, and a flow silicon oxide film having a small moisture content and excellent in dielectric constant and filling property is used to prevent the diffusion of moisture, thereby preventing corrosion of the metal film, The operation speed is improved.

Description

반도체 소자의 층간 절연막 및 그 제조방법Interlayer insulating film of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2c도는 본 발명의 반도체 소자의 층간 절연막 제조방법을 공정 순서적으로 나타낸 도면.FIGS. 2A to 2C are diagrams showing a process sequence of a method for manufacturing an interlayer insulating film of a semiconductor device of the present invention. FIG.

Claims (11)

트랜지스터 및 트랜지스터 각각의 접합 영역을 전기적으로 연결시키는 금속 배선이 형성된 실리콘 기판 상부에 실리콘 기판 성분과 제1원자가 포함되고, 금속 배선을 절연시키는 제1산화막; 상기 제1산화막 상부에 형성되고, 평탄화 된 표면을 갖으며, 실리콘 기판 성분과 제1성분 및 제2성분을 포함하는 평탄화 절연막; 상기 평탄화 절연막 상부에 제1산화막과 동일한 성분을 갖는 제2산화막을 포함하는 것을 특징으로 하는 반도체 소자의 층간 절연막.A first oxide film including a silicon substrate component and a first atom on a silicon substrate on which a metal interconnection for electrically connecting junction regions of the transistor and the transistor is formed and insulates the metal interconnection; A planarization insulating film formed on the first oxide film and having a planarized surface, the planarization insulating film including a silicon substrate component, a first component and a second component; And a second oxide film having the same composition as the first oxide film on the planarization insulating film. 제1항에 있어서, 상기 제1성분은 O2인 것을 특징으로 하는 반도체 소자의 층간 절연막.The interlayer insulating film of a semiconductor device according to claim 1, wherein the first component is O2. 제1항에 있어서, 상기 제2 성분은 SF4인 것을 특징으로 하는 반도체 소자의 층간 절연막.The interlayer insulating film of a semiconductor device according to claim 1, wherein the second component is SF4. 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 층간 평탄화막은 SiOF막인 것을 특징으로 하는 반도체 소자의 층간 절연막.The interlayer insulating film of a semiconductor device according to any one of claims 1 to 3, wherein the interlayer planarizing film is an SiOF film. 제1항에 있어서, 상기 제1산화막의 두께는 100 내지 1500Å인 것을 특징으로 하는 반도체 소자의 층간 절연막.The interlayer insulating film of a semiconductor device according to claim 1, wherein the first oxide film has a thickness of 100 to 1500 ANGSTROM. 제1항에 있어서, 상기 제2산화막의 두께는 3000 내지 5000Å인 것을 특징으로 하는 반도체 소자의 층간 절연막.The interlayer insulating film of a semiconductor device according to claim 1, wherein the thickness of the second oxide film is 3000 to 5000 ANGSTROM. 트랜지스터 및 트랜지스터 각각의 접합 영역을 전기적으로 연결시키는 금속 배선이 형성된 실리콘 기판 상부에 제1산화막을 형성하는 단계; 상기 제1산화막 상부에 플로우르화 실리콘 산화막을 증착하는 단계; 상기 플로우르화 실리콘 산화막이 평탄한 표면을 갖도록 제거하는 단계; 및 상기 구조물 상부에 제2산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 층간 절연막의 제조방법.Forming a first oxide film on a silicon substrate on which a metal interconnection electrically connecting junction regions of the transistor and the transistor is formed; Depositing a silicon oxide oxide film on the first oxide film; Removing the floating silicon oxide film to have a flat surface; And forming a second oxide film on an upper surface of the structure. 제7항에 있어서, 상기 제1산화막과 제2산화막은 플라즈마 인가 화학 기상 증착 방식에 의하여 형성하는 것을 특징으로 하는 반도체 소자의 층간 절연막의 제조방법.8. The method of claim 7, wherein the first oxide layer and the second oxide layer are formed by a plasma-assisted chemical vapor deposition method. 제7항에 있어서, 상기 플로우르화 실리콘 산화막의 증착 두께는 9000 내지 10000Å인 것을 특징으로 하는 반도체 소자의 층간 절연막의 제조방법.8. The method of claim 7, wherein the deposited silicon nitride oxide film has a thickness of 9000 to 10000 angstroms. 제7항에 있어서, 상기 평탄한 표면을 갖는 플로우르화 실리콘막을 형성하기 위하여는, 플로우화 실리콘막의 표면을 화학적 기계적 연마하는 것을 특징으로 하는 반도체 소자의 층간 절연막의 제조방법.The method for manufacturing an interlayer insulating film of a semiconductor device according to claim 7, wherein the surface of the siliconized flow film is chemically and mechanically polished to form the silicon oxide film having a flat surface. 제7항에 있어서, 상기 플로우르화 실리콘 산화막은 고밀도 플라즈마인가 화학 기상 증착 방식에 의하여 형성하는 것을 특징으로 하는 반도체 소자의 층간 절연막의 제조방법.The method of manufacturing a semiconductor device according to claim 7, wherein the silicon fluoride oxide film is formed by a high density plasma or chemical vapor deposition method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024510A 1996-06-27 1996-06-27 Interlayer insulating film of semiconductor device and manufacturing method thereof KR980005827A (en)

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