KR980005035A

KR980005035A - Mask ROM with Address Multiplexing Device

Info

Publication number: KR980005035A
Application number: KR1019960022886A
Authority: KR
Inventors: 윤연중
Original assignee: 문정환; 엘지반도체 주식회사
Priority date: 1996-06-21
Filing date: 1996-06-21
Publication date: 1998-03-30

Abstract

본 발명은 마스크 롬의 어드레스 입력장치에 관한 것으로, 특히 어드레스 멀티플렉싱을 제어하기 위한 제어신호가 없는 제품에 적당하도록 한 어드레스 멀티플렉싱 장치가 포함된 마스크 롬에 관한 것으로, 입력되는 어드레스신호(ADD)를 제어신호(CRL2)에 의해 정해진 시간간격으로 X 어드레스 신호(XADD)와 Y 어드레스 신호(YADD)를 번갈아 입력받음과 아울러 어드레스 천이검출신호의 총합(ATD')을 발생하여 출력하는 어드레스 버퍼(200)와, 상기 어드레스 버퍼(200)로부터 출력되는 어드레스 천이검출 신호의 총합(ATD')을 인가받아 X 어드레스 신호(XADD)와 Y 어드레스 신호(YADD)의 입력여부를 결정하는 제어신호(CTL2)를 출력하는 제어부(260)를 더 포함하여 구성함으로써 단순히 X 어드레스 신호와 Y 어드레스 신호를 정해진 시간에 입력받는 것만으로 어드레스 신호를 멀티플렉싱행함으로써 외부의 다른 제어신호가 굳이 필요하지 않으므로 별도의 입력 패드 또는 핀이 필요없게되어 제품의 소형화가 가능한 효과가 있게된다.The present invention relates to an address input device of a mask ROM, and more particularly to a mask ROM including an address multiplexing device suitable for a product without a control signal for controlling address multiplexing. An address buffer 200 for alternately inputting the X address signal XADD and the Y address signal YADD at a time interval determined by the signal CRL2, and generating and outputting the sum total of the address transition detection signals ATD '; And outputting a control signal CTL2 for determining whether the X address signal XADD and the Y address signal YADD are input by receiving the sum ADT 'of the address transition detection signals output from the address buffer 200. The controller 260 further includes an address signal by simply receiving the X address signal and the Y address signal at a predetermined time. The multiplexing process eliminates the need for external control signals and eliminates the need for separate input pads or pins, thereby miniaturizing the product.

Description

Mask ROM with Address Multiplexing Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명 어드레스 멀티플렉싱 장치가 포함된 마스크 롬의 내부 블럭도.2 is an internal block diagram of a mask ROM including the address multiplexing device of the present invention.

제3도는 제2도 어드레스 버퍼의 내부 회로도.3 is an internal circuit diagram of the FIG. 2 address buffer.

제4도는 제2도 제어부의 내부 회로도.4 is an internal circuit diagram of the control unit of FIG.

Claims

In a mask ROM that receives address data and separates the data into the X address signal and the Y address signal, respectively, and reads out the data in the memory cell, the input address signal ADD is X at a time interval determined by the control signal CTL2. An address buffer 200 that receives the address signal XADD and the Y address signal YADD alternately, and generates and outputs the sum ADT 'of the address transition detection signal; and an address output from the address buffer 200. And a control unit 260 for outputting a control signal CTL2 for determining whether to input the X address signal XADD and the Y address signal YADD by receiving the sum of the transition detection signals ADT '. Mask ROM containing an address multiplexing device.

2. The address buffer 200 of claim 1, wherein the address buffer 200 is an oragate 201 configured to logically combine an input address signal ADD and an element enable signal EN, and the oragate by a control signal CTL2. A transfer gate 202 that determines whether the output of the 201 is transferred, and an output of the transfer gate 202 is received and latched to output the X address signal XADD through the output inverters I2 and I3. An output transition I4, I5 for receiving a latch 203, an output of the ora gate 201 and outputting a Y address signal YADD, and an address transition detection signal for receiving an output of the ora gate 201 An address transition detection generation unit 204 for generating and outputting a signal, an AND gate 206 for receiving a logical combination of the address transition detection generation unit 204 and a control signal CTL2, and a latch of the latch 203. Output is applied to generate and output address transition detection signal. An oragate 207 that receives the output of the address transition detection generation unit 205 and the outputs of the AND gate 206 and the address transition detection generation unit 205, and logically combines the outputs of the address detection signals ADT '. Mask ROM containing an address multiplexing device, characterized in that consisting of).

2. The control unit 260 of claim 1, wherein the control unit 260 receives a total of the address detection signals ADT 'and delays the predetermined time, and a total of the outputs of the delay units 261 and the address detection signals ADT. And a delay unit 262 for logically combining ') to output a control signal CTL1 of the sense amplifier NOR1, a delay unit 262 for delaying a predetermined time by receiving the sum ARD' of the address detection signal, and the delay. The OA gate 263 logically combines the output of the unit 262 with the sum ADT 'of the address detection signal, and the output of the control signal CTL1 and the OA gate 263 is logically combined to receive a control signal ( And a mask ROM comprising an address multiplexing device, characterized in that it comprises an orifice 264 that outputs CTL2).

※ Note: The disclosure is based on the initial application.