KR980005019A - Method for erasing a flash memory cell - Google Patents

Method for erasing a flash memory cell Download PDF

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Publication number
KR980005019A
KR980005019A KR1019960025549A KR19960025549A KR980005019A KR 980005019 A KR980005019 A KR 980005019A KR 1019960025549 A KR1019960025549 A KR 1019960025549A KR 19960025549 A KR19960025549 A KR 19960025549A KR 980005019 A KR980005019 A KR 980005019A
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KR
South Korea
Prior art keywords
voltage
erase
power supply
memory cell
erasing
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Application number
KR1019960025549A
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Korean (ko)
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KR100223263B1 (en
Inventor
김대현
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019960025549A priority Critical patent/KR100223263B1/en
Publication of KR980005019A publication Critical patent/KR980005019A/en
Application granted granted Critical
Publication of KR100223263B1 publication Critical patent/KR100223263B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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  • Read Only Memory (AREA)

Abstract

본 발명은 플래쉬 메모리셀의 소거동작시 전원전압(Vcc)의 증가에 따라 반비례 하는 소거전압을 셀에 인가하여 고전압(High Vcc)에서도 저전압(Low Vcc)에서와 같은 셀 스트레스(Stress)를 주어 소거동작을 하고, 확인동작시에도 기준셀(Refference Cell)의 기준전류를 전원전압에 따라 일정하게 만들어 주어 전원전압에 따라 일정한 소거동작이 되도록 한 플래쉬 메모리셀의 소거방법에 관해 개시된다.The present invention applies an erase voltage in inverse proportion to an increase of a power source voltage Vcc in an erase operation of a flash memory cell to give a cell stress such as a low voltage (Low Vcc) even at a high voltage (High Vcc) And a reference current of a reference cell is made constant in accordance with a power supply voltage in a verify operation so that a constant erase operation is performed according to a power supply voltage.

Description

플래쉬 메모리 셀의 소거방법Method for erasing a flash memory cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 플래쉬 메모리셀의 소거방법을 설명하기 위해 도시한 블럭도.FIG. 1 is a block diagram for explaining a method of erasing a flash memory cell according to the present invention; FIG.

Claims (5)

메모리셀의 소거동작에 있어서, 메인 메모리셀 블럭의 메모리셀에 가해지는 네가티브 챠지펌프의 출력전압이 레귤레이터를 통해 일정한 소거동작 전압으로 조절되도록 하고, 상기 일정하게 조절된 소거동작 전압에 의해 상기 메인 메모리셀의 소거동작이 이루어 지도록 하는 것을 특징으로 하는 플래쉬 메모리셀의 소거방법.The erasing operation voltage of the main memory cell block is set to a predetermined erasing operating voltage through the regulator so that the output voltage of the negative charging pump applied to the memory cell of the main memory cell block is adjusted to a constant erasing operating voltage, The erase operation of the cell is performed. 제1항에 있어서, 상기 레귤레이터를 통해 얻어지는 소거동작 전압은 전원정압 제어부의 출력전압을 입력으로 하는 고전압 트랜지스터의 동작에 따라 소거전압이 전원전압에 반비례하게 하여 얻어지도록 하고, 상기 전원전압에 반비례하게 얻어진 소거전압에 의해 소거동작이 이루어 지도록 하는 것을 특징으로 하는 플래쉬 메모리셀의 소거방법.The method of claim 1, wherein the erase operation voltage obtained through the regulator is obtained in such a manner that the erase voltage is inversely proportional to the power supply voltage in accordance with the operation of the high voltage transistor having the output voltage of the power supply constant voltage control unit as an input, And the erase operation is performed by the erase voltage obtained. 제1항에 있어서, 상기 레귤레이터를 통해 얻어지는 소거동작 전압은 고전압 트랜지스터의 N-웰과 소오스전극을 접지단자에 연결하여 얻어지도록 하고, 상기 얻어진 소거 동작 전압에 의해 소거동작이 이루어 지도록 하는 것을 특징으로 하는 플래쉬 메모리 셀의 소거방법.2. The method according to claim 1, wherein an erase operation voltage obtained through the regulator is obtained by connecting an N-well and a source electrode of a high-voltage transistor to a ground terminal, and an erase operation is performed by the obtained erase operation voltage Of the flash memory cell. 제2항에 있어서, 상기 전원전압 제어부의 출력전압은 NMOS 트랜지스터의 문턱전압을 이용하여 전원전압을 강하시키고, 상기 강하된 전원전압에 의해 소거동작이 이루어 지도록 하는 것을 특징으로 하는 플래쉬 메모리셀의 소거방법.3. The flash memory cell of claim 2, wherein the output voltage of the power supply voltage control unit lowers the power supply voltage by using a threshold voltage of the NMOS transistor, and the erasing operation is performed by the lowered power supply voltage Way. 고전압에 의한 소거확인 동작시 기준셀의 셀렉트게이트와 플로팅 게이트에 전원전압에 무관한 독출전압을 공급하여 소거확인 동작이 이루어지도록 하는 것을특징으로 하는 플래쉬 메모리셀의 소거방법.Wherein the erase verify operation is performed by supplying a read voltage independent of the power supply voltage to the select gate and the floating gate of the reference cell during the erase verify operation by the high voltage. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025549A 1996-06-29 1996-06-29 Erasing method of flash memory cell KR100223263B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025549A KR100223263B1 (en) 1996-06-29 1996-06-29 Erasing method of flash memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025549A KR100223263B1 (en) 1996-06-29 1996-06-29 Erasing method of flash memory cell

Publications (2)

Publication Number Publication Date
KR980005019A true KR980005019A (en) 1998-03-30
KR100223263B1 KR100223263B1 (en) 1999-10-15

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KR1019960025549A KR100223263B1 (en) 1996-06-29 1996-06-29 Erasing method of flash memory cell

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100509199B1 (en) * 1998-12-29 2005-10-26 주식회사 하이닉스반도체 How to program and erase flash memory cells
KR100735009B1 (en) * 2005-08-30 2007-07-03 삼성전자주식회사 Flash memory device capable of reducing erase time

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100830575B1 (en) 2006-09-26 2008-05-21 삼성전자주식회사 Flash memory device and multi-block erase method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100509199B1 (en) * 1998-12-29 2005-10-26 주식회사 하이닉스반도체 How to program and erase flash memory cells
KR100735009B1 (en) * 2005-08-30 2007-07-03 삼성전자주식회사 Flash memory device capable of reducing erase time

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KR100223263B1 (en) 1999-10-15

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