KR980005014A

KR980005014A - Burst counter and its carry method

Info

Publication number: KR980005014A
Application number: KR1019970026471A
Authority: KR
Inventors: 김광일; 박희철
Original assignee: 윤종용; 삼성전자 주식회사
Priority date: 1996-06-26
Filing date: 1997-06-23
Publication date: 1998-03-30
Also published as: KR100455368B1; KR980004988A

Abstract

본 발명은 버스트 카운터(Burst Counter) 및 그 캐리(carry) 발생 방법에 관한 것이다. 본 발명은 버스트 시작 신호와 버스트 지속 신호가 인에이블(enable)될 때 버스트 모드로 진입하는 버스터 카운터에 있어서, 제1 버스트 클럭 발생부, 제2 내부 클럭 발생부, 캐리 신호 제어부, 셀 제어부 및 제1 셀 내지 제3 셀들을 구비한다. 상기 제1 버스트 클럭 발생부는 상기 버스트 시작 신호와 내부 클럭 신호에 응답하여 제1 버스트 클럭 신호를 발생한다. 상기 제2 내부 클럭 발생부는 상기 버스트 지속 신호와 상기 내부 클럭 신호에 응답하여 제2 내부 클럭 신호를 발생한다. 상기 캐리 신호 제어부는 상기 제1 버스트 클럭 신호와 상기 제2 내부 클럭 신호에 응답하여 캐리 제어 신호를 발생한다. 상기 셀 제어부는 버스트 모드를 선택하는 버스트 모드 신호와 버스트 시작 어드레스 신호와 캐리 신호와 상기 제1 내지 제2 내부 클럭 신호들에 응답하여 제1셀 내지 제3 셀 제어 신호들을 발생한다. 상기 제1 셀 내지 제3 셀들은 상기 제1 셀 내지 제3 셀 제어 신호들과 상기 버스트 시작 어드레스 신호와 상기 버스트 시작 신호 및 상기 내부 클럭 신호에 응답하여 각각 상기 캐리 신호와 최저 비트 어드레스 신호 및 최고 비트 어드레스 신호를 발생한다. 상기 캐리 신호는 상기 제1 버스트 클럭 신호 또는 상기 제2 내부 클럭 신호가 디세이블(disable)될 때 펄스 신호로 발생하는 것을 반복한다.The present invention relates to a burst counter and a method of generating a carry thereof. The present invention provides a burst counter for entering a burst mode when a burst start signal and a burst sustain signal are enabled, comprising: a first burst clock generator, a second internal clock generator, a carry signal controller, a cell controller, and a first controller; 1 to 3 cells. The first burst clock generator generates a first burst clock signal in response to the burst start signal and an internal clock signal. The second internal clock generator generates a second internal clock signal in response to the burst sustain signal and the internal clock signal. The carry signal controller generates a carry control signal in response to the first burst clock signal and the second internal clock signal. The cell controller generates first to third cell control signals in response to a burst mode signal for selecting a burst mode, a burst start address signal, a carry signal, and the first to second internal clock signals. The first to third cells are the carry signal, the lowest bit address signal, and the highest in response to the first to third cell control signals, the burst start address signal, the burst start signal, and the internal clock signal, respectively. Generates a bit address signal. The carry signal is repeatedly generated as a pulse signal when the first burst clock signal or the second internal clock signal is disabled.

Description

Burst counter and its carry method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 바람직한 실시예에 따른 버스트 카운터의 회로도.5 is a circuit diagram of a burst counter in accordance with a preferred embodiment of the present invention.

Claims

A first burst clock generator configured to generate a first burst clock signal in response to a burst start signal and an internal clock signal at which a burst mode is started when enabled; A second internal clock generator configured to generate a second internal clock signal in response to the burst sustain signal and the internal clock signal when the burst mode is enabled; A carry signal controller configured to generate a carry control signal in response to the first burst clock signal and the second internal clock signal; A cell controller configured to generate first cell to third cell control signals in response to a burst mode signal, a burst start address signal, a carry signal, and the first to second internal clock signals to select a burst mode; A first cell generating the carry signal in response to the first cell control signal, the carry control signal, the complementary signal of the carry control signal, the burst start signal, and the internal clock signal; A second cell generating a lowest bit burst address signal in response to the first to second internal clock signals, a lower burst start address signal of the burst start address signal, the burst start signal, and the internal clock signal; And a third cell generating a highest bit burst address signal in response to the third cell control signals, an upper burst start address signal of the burst start address signal, the burst start signal, and the internal clock signal. The carry signal is enabled when the first burst clock signal is disabled and then repeatedly disabled and enabled every time the second internal clock signal is disabled.

The apparatus of claim 1, wherein the first burst clock generator comprises: a burst start signal controller configured to generate a first control signal in response to the burst start signal and the internal clock signal; An inverter chain configured to delay and invert the first control signal by a predetermined time; A NAND gate configured to receive an output of the inverter chain and the first control signal and generate a complementary signal of the first burst clock signal; And an inverter for inverting the output of the NAND gate to generate the first burst clock signal.

The burst counter of claim 2, wherein the burst start signal controller is a NAND gate.

The method of claim 1, wherein the output of the second internal clock generator is logic high when any of the burst sustain signal and the internal clock signal are logic low, and the burst sustain signal and the internal clock signal are mode logic high. And a burst sustain signal controller whose output is logic low; An inverter chain configured to delay and invert the output of the burst sustain signal controller by a predetermined time; A NAND gate having an output of the burst sustain signal controller and an input of the inverter chain; And an inverter for inverting the output of the NAND gate to generate the second internal clock signal.

The burst counter of claim 4, wherein the burst sustain signal controller is a NAND gate.

2. The method of claim 1, wherein if any one of the first burst clock signal and the second internal clock signal is logic high at an output terminal of the first burst clock generator and the second internal clock generator, the logic signal is set to be logic low. And a second controller configured to generate a second control signal that is logic high when the burst clock signal and the second internal clock signal are both logic low, and a complementary signal of the second control signal.

7. The apparatus of claim 6, wherein the second control unit comprises: a noah gate for inputting the first burst clock signal and the second internal clock signal and generating the second control signal; And an inverter connected to the NOR gate and inverting the second control signal to generate a complementary signal of the second control signal.

The apparatus of claim 1, wherein the carry signal controller comprises: an inverter chain configured to delay and invert the second control signal by a predetermined time; A NAND gate having an output of the inverter chain and the second control signal as an input and generating a complementary signal of the carry control signal; And an inverter for generating the carry signal by inverting the output of the NAND gate.

The display apparatus of claim 1, wherein the cell controller comprises: a first inverter configured to invert the burst mode signal; A second inverter for inverting the burst start address signal; A NAND gate generating the first cell control signal having an output of the first inverter and an output of the second inverter as inputs; A NOR gate inverting and ORing the complementary signal of the burst mode signal and the first burst clock signal; Another NAND gate inverting and outputting the output of the NOR gate and the second internal clock signal; Another NOR gate inverting and logic output of the other NAND gate and the carry signal to generate the third cell control signal; And a third inverter for inverting the output of the other NOR gate to generate another third sal control signal.

The semiconductor device of claim 1, wherein the first cell comprises: a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the first cell control signal; A second PMOS transistor having a source connected to the drain of the first PMOS transistor and having a gate connected to a signal generated by inverting and performing the burst start signal and the internal clock signal; A first NMOS transistor having a drain connected to a drain of the second PMOS transistor and having a gate connected to a signal generated by an AND of the burst start signal and the internal clock signal; A second NMOS transistor having a drain connected to a source of the first NMOS transistor, a gate connected to the first cell control signal, and a source connected to a ground voltage; A third PMOS transistor having a source connected to the power supply voltage and a gate connected to a drain of the second PMOS transistor; A fourth PMOS transistor having a source connected to a drain of the third PMOS transistor and a gate connected to the carry control signal; A third NMOS transistor having a drain connected to a drain of the fourth PMOS transistor and a gate connected to a complementary signal of the carry control signal; A fourth NMOS transistor having a drain connected to a source of the third NMOS transistor, a gate connected to a gate of the third PMOS transistor, and a source connected to a ground voltage; A latch connected to the drain of the fourth PMOS transistor; An inverter chain connected to the latch; A fifth PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverter chain; A sixth PMOS transistor having a source connected to a drain of the fifth PMOS transistor and a gate connected to a complementary signal of the carry control signal; A fifth NMOS transistor having a drain connected to a drain of the sixth PMOS transistor and a gate connected to the carry control signal; A sixth NMOS transistor having a drain connected to a source of the fifth NMOS transistor, a gate connected to the inverter chain, and a source connected to a ground voltage; And another latch connected in common with the drain of the sixth PMOS transistor and the drain of the second PMOS transistor to generate the carry signal.

The semiconductor device of claim 1, wherein the second cell comprises: a first PMOS transistor having a source connected to a power supply voltage and a gate connected to a lower burst start address signal of the burst start address signals; A second PMOS transistor having a source connected to the drain of the first PMOS transistor and having a gate connected to a signal generated by inverting and performing the burst start signal and the internal clock signal; A first NMOS transistor having a drain connected to a drain of the second PMOS transistor and having a gate connected to a signal generated by an AND of the burst start signal and the internal clock signal; A second NMOS transistor having a drain connected to a source of the first NMOS transistor, a gate connected to the lower burst start address signal, and a source connected to a ground voltage; A third PMOS transistor having a source connected to the power supply voltage and a gate connected to a drain of the second PMOS transistor; A fourth PMOS transistor having a source connected to a drain of the third PMOS transistor, and a gate connected to a signal generated by ORing the first burst clock signal and the second internal clock signal; A third NMOS transistor having a drain connected to a drain of the fourth PMOS transistor and having a gate connected to a signal generated by inverting and logically combining the first burst clock signal and the second internal clock signal; A fourth NMOS transistor having a drain connected to a source of the third NMOS transistor, a gate connected to a gate of the third PMOS transistor, and a source connected to a ground voltage; A latch connected to the drain of the fourth PMOS transistor; An inverter chain connected to the latch; A fifth PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverter chain; A sixth PMOS transistor having a source connected to a drain of the fifth PMOS transistor and a gate connected to the second cell control signal; A fifth NMOS transistor having a drain connected to a drain of the sixth PMOS transistor and a gate connected to a signal in which the second cell control signal is inverted; A sixth NMOS transistor having a drain connected to a source of the fifth NMOS transistor, a gate connected to the inverter chain, and a source connected to a ground voltage; And another latch connected in common to the drain of the sixth PMOS transistor and the drain of the second PMOS transistor and generating the lowest bit address signal.

The semiconductor device of claim 1, wherein the third cell comprises: a first PMOS transistor having a source connected to a power supply voltage and a gate connected to the burst start address signal; A second PMOS transistor having a source connected to the drain of the first PMOS transistor and having a gate connected to a signal generated by inverting and performing the burst start signal and the internal clock signal; A first NMOS transistor having a drain connected to a drain of the second PMOS transistor and having a gate connected to a signal generated by an AND of the burst start signal and the internal clock signal; A second NMOS transistor having a drain connected to a source of the first NMOS transistor, a gate connected to the burst start address signal, and a source connected to a ground voltage; A third PMOS transistor having a source connected to the power supply voltage and a gate connected to a drain of the second PMOS transistor; A fourth PMOS transistor having a source connected to a drain of the third PMOS transistor and a gate connected to the third cell control signal; A third NMOS transistor having a drain connected to a drain of the fourth PMOS transistor and a gate connected to a signal in which the third cell control signal is inverted; A fourth NMOS transistor having a drain connected to a source of the third NMOS transistor, a gate connected to a gate of the third PMOS transistor, and a source connected to a ground voltage; A latch connected to the drain of the fourth PMOS transistor; An inverter chain connected to the latch; A fifth PMOS transistor having a source connected to the power supply voltage and a gate connected to the inverter chain; A sixth PMOS transistor having a source connected to a drain of the fifth PMOS transistor and a gate connected to the third cell control signal; A fifth NMOS transistor having a drain connected to a drain of the sixth PMOS transistor and a gate connected to a signal in which the third cell control signal is inverted; A sixth NMOS transistor having a drain connected to a source of the fifth NMOS transistor, a gate connected to the inverter chain, and a source connected to a ground voltage; And another latch connected in common with the drain of the sixth PMOS transistor and the drain of the second PMOS transistor to generate the highest bit address signal.

Enabling the first burst clock signal when the internal clock signal is enabled and disabled in a state where the burst start signal at which the burst mode is started when enabled is enabled; Enabling a carry signal when the first burst clock signal is disabled; Enabling a second internal clock signal when the internal clock signal is enabled and disabled while a burst sustain signal in which a burst mode that continues burst mode is enabled is enabled; Disabling the carry signal when the second internal clock signal is disabled; And the second internal clock signal is generated each time the internal clock signal is enabled and disabled while the burst sustain signal is enabled, and the carry signal is generated each time the second internal clock signal is disabled. And repeatedly disabling and disabling the burst counter.

14. The method of claim 13, wherein enabling the carry signal comprises: enabling and disabling a control signal (KKOB) when the first burst clock is enabled and then disabled; Enabling a carry control signal when the control signal KKOB is disabled; And enabling the carry signal when the carry control signal is enabled.

14. The method of claim 13, wherein disabling the carry signal comprises: enabling and disabling a control signal (KKOB) when the second internal clock is enabled and then disabled; Enabling a carry control signal when the control signal KKOB is disabled; And disabling the carry signal when the carry control signal is enabled.

※ Note: The disclosure is based on the initial application.