KR980004999A - A semiconductor memory device having a fast data access function - Google Patents

A semiconductor memory device having a fast data access function Download PDF

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Publication number
KR980004999A
KR980004999A KR1019960025746A KR19960025746A KR980004999A KR 980004999 A KR980004999 A KR 980004999A KR 1019960025746 A KR1019960025746 A KR 1019960025746A KR 19960025746 A KR19960025746 A KR 19960025746A KR 980004999 A KR980004999 A KR 980004999A
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KR
South Korea
Prior art keywords
data
memory device
switch means
semiconductor memory
output
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KR1019960025746A
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Korean (ko)
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KR100225950B1 (en
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박종훈
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김주용
현대전자산업 주식회사
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Priority to KR1019960025746A priority Critical patent/KR100225950B1/en
Publication of KR980004999A publication Critical patent/KR980004999A/en
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Publication of KR100225950B1 publication Critical patent/KR100225950B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 데이타 경로를 병렬로 배치하여 데이타를 동시에 엑세스해 놓은 다음에 순차적으로 출력하도록 함으로써 종래의 것에 비해 n배의 빠른 데이타 엑세스를 실현시킨 반도체 메모리 장치에 관한 것으로, 다수의 메모리 셀로 구성된 셀 어레이 블럭과, 1개의 컬럼 어드레스를 받아들여 동시에 n개의 셀을 선택 구동하기 위한 칼럼 디코더 수단과, 상기 n개의 셀에 대응하게 구성된 n개의 데이타 버스라인과, 상기 n개의 데이타 버스라인을 순차적으로 n개의 제어신호를 이용 데이타를 전달하는 제1 스위치 수단과, 상기 제1 스위치 수단에 의해 전달된 데이타를 감지·증폭하는 데이타버스 센스앰프와, 상기 데이타버스 샌스앰프로부터 전달된 데이타를 버퍼링하여 출력하는 제1 데이타 출력버퍼와, 상기 제1 데이타 출력버퍼로부터 출력된 신호를 n개의 샘플링 신호에 의해 래치시키는 n개의 제2 스위칭 수단과, 상기 제2 스위치 수단으로부터 출력된 신호를 각각 버퍼링하여 데이타 출력핀으로 출력하기 위한 n개로 이루어진 제2 데이타 출력버퍼를 구비하였다.The present invention relates to a semiconductor memory device in which data paths are arranged in parallel to access data at the same time and sequentially output, thereby realizing n times as fast data access as compared with the conventional semiconductor memory device. A column decoder means for receiving one column address and selecting and driving n cells at the same time; n data bus lines configured corresponding to the n cells; and n data bus lines sequentially connected to n A first switch means for transmitting data using a control signal, a data bus sense amplifier for sensing and amplifying data transmitted by the first switch means, and a data bus sense amplifier for buffering and outputting data transmitted from the data bus sans amp 1 data output buffer, and a signal output from the first data output buffer is n And n second data output buffers for buffering the signals output from the second switch means and outputting the signals to the data output pins.

Description

빠른 데이터 엑세스 기능을 갖는 반도체 메모리 장치A semiconductor memory device having a fast data access function

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명의 일실시예에 의한 시리얼 엑세스 메모리의 구성도.FIG. 3 is a block diagram of a serial access memory according to an embodiment of the present invention; FIG.

제4도는 제3도의 동작 타이밍도.FIG. 4 is an operation timing diagram of FIG. 3; FIG.

Claims (2)

반도체 메모리 장치에 있어서, 다수의 메모리 셀로 구성된 셀 어레이 블럭과, 1개의 컬럼 어드레스를 받아들여 동시에 n개의 셀을 선택 구동하기 위한 컬럼 디코더 수단과, 상기 n개의 셀에 대응하게 구성된 n개의 데이타 버스라인과, 상기 n개의 데이타 버스라인을 순차적으로 n개의 제어신호를 이용 데이타를 전달하는 제1 스위치 수단과, 상기 제1 스위치 수단에 의해 전달된 데이타를 감지·증폭하는 데이타버스 센스앰프와, 상기 데이타버스 센스앰프로부터 전달된 데이타를 버퍼링하여 출력하는 제1 데이타 출력버퍼와, 상기 제1 데이타 출력버퍼로부터 출력된 신호를 n개의 샘플링 신호에 의해 래치시키는 n개의 제2 스위치 수단과, 상기 제2 스위치 수단으로부터 출력된 신호를 각각 버퍼링하여 데이타 출력핀으로 출력하기 위한 n개로 이루어진 제2 데이타 출력버퍼를 구비하는 것을 특징으로 하는 빠른 데이타 엑세스 기능을 갖는 반도체 메모리 장치.A semiconductor memory device comprising: a cell array block composed of a plurality of memory cells; column decoder means for receiving one column address and selecting and driving n cells at the same time; and n data bus lines A data bus sense amplifier for sensing and amplifying the data transmitted by the first switch means, and a data bus sense amplifier for transmitting and receiving the data, A first data output buffer for buffering and outputting data transmitted from the bus sense amplifier; n second switch means for latching the signal output from the first data output buffer by n sampling signals; Means for buffering the signals output from the means and outputting the signals to the data output pins, And an output buffer connected to the data output buffer. 제1항에 있어서, 상기 제1 스위치 수단 및 제2 스위치 수단은 전달 게이트인 것을 특징으로 하는 빠른 데이타 엑세스 기능을 갖는 반도체 메모리 장치.The semiconductor memory device according to claim 1, wherein the first switch means and the second switch means are transfer gates. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025746A 1996-06-29 1996-06-29 Memory device fast accessible to the data KR100225950B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025746A KR100225950B1 (en) 1996-06-29 1996-06-29 Memory device fast accessible to the data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025746A KR100225950B1 (en) 1996-06-29 1996-06-29 Memory device fast accessible to the data

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KR980004999A true KR980004999A (en) 1998-03-30
KR100225950B1 KR100225950B1 (en) 1999-10-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315042B1 (en) * 1999-12-23 2001-11-29 박종섭 Virtual channel dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315042B1 (en) * 1999-12-23 2001-11-29 박종섭 Virtual channel dram

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Publication number Publication date
KR100225950B1 (en) 1999-10-15

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